Method and system for low-cost and high performance power factor correction

ABSTRACT

A Low Cost High Performances Power Factor Correction method, system and apparatus, comprising a AC power source (Vac) able to provide a low frequency supply signal, a low frequency pass filter circuit (LPF) able to protect the power source (Vac) against reverse high frequency signal noise, a rectifier circuit (BR) able to provide a fully rectify low frequency supply signal, a high frequency DC/DC converter circuit (PFC-LSC) able to convert the fully rectified low frequency supply signal into a rectified high frequency supply signal and having the capability to absorb and deliver at any moment a current amount contingent and linearly proportional in amplitude to its supply voltage amount and/or its driving pulses duty cycle ratio, a small signal controller circuit (PFC-SSC) able to control the converter circuit and a complex load circuit (CL) including at least one capacitor able to storage the rectified high frequency supply signal, so the small signal controller circuit (PFC-SSC) controls the large signal converter circuit (PFC-LSC) by means of a pulse width modulation driving signal consisting of trains of pulses constant in frequency and duty cycle during a period of time equal or longer than one of the AC power source (Vac) supply signal semi-cycle period so during each the supply signal&#39;s semi-cycle period, as long as the controlling pulse is constant, the current amount absorbed by the large signal circuit (PFC-LSC) from the AC power source (Vac) is contingent and linearly proportional to the AC power source&#39;s voltage amount only, so the AC power source&#39;s output current and voltage amount follows an identical graphic shape and so the energy transfer&#39;s power factor parameter of the AC power source (Vac) and the complex load (CL) system is improved near unity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a Power Factor Correction (PFC)Circuit. More particularly, the present invention relates to a new wayof managing and controlling an Active PFC System, not by using a classic“Multiplier” concept and its related circuit, but by using an original“Constant Pulse—Proportional Current” (CPPC) conversion concept,embedded via several electronic circuits that have a novel configurationand/or architecture.

Implemented in a standard “bulk capacitor-input rectifier” power supply,this invention provides low cost solutions for improving the PowerFactor to over 0.999 (from typically PF=0.6-0.7) and reducing the TotalHarmonic Distortion (THC) down to less than 1% (from typicallyTHD=75-115%).

2. Introduction

In the process of transferring AC electrical power from a generator to aload via different converting devices, in addition to the Efficiency,the Power Factor is also a very important parameter.

The Efficiency parameter (Eff=Pout/Pin) provides information about thepercentage of the inputted electrical power that has been transferred,by a specific electrical device, to its output load. Usually, the restof the electrical power, which has not been delivered to the load, istransformed into heat, dissipated by the electrical device's parts.

The Power Factor parameter is not related at all to an electricaldevice's in/out transfer of the electrical energy (i.e. its efficiency),however it provides information about how well has been managed the“Real Power” absorbed by an electrical device, versus the “ApparentPower” requested by that device from its electrical generator.

The Real Power, defined by the following relation:P(Watts)=[1:T×S(Vi×li,dt)]is the watts power absorbed by a device from its electrical generatorand its amount value is proportional to the integral of the voltage andcurrent product/time unit.

The Apparent Power (or RMS Power), defined by the following relation:P(VA)=Vrms×Irmsis the Volt-Amperes power requested by a device from its electricalgenerator and its amount's value is proportional to the product of therms Voltage and the rms Current.

Accordingly, the Power Factor (PF) parameter is defined by the followingrelation:PF=[1:T×S(Vi×li,dt)]:(Vrms×Irms); W/VA<1respectively the Real Power to the Apparent Power (W/VA) ratio.

When an electrical circuit comprises resistive (or linear) devices only(see FIG. 1), such as heaters, incandescent bulbs, etc., the circuitcurrent's amplitude/time graph is a sine wave identical in shape andfaze with the input voltage's graph (see FIG. 26,A), fact which make theApparent Power amount equal to the Real Power's amount. In thissituation, according to the above equation, the PF=1.

When an electrical circuit comprises, in addition to resistive devices,some reactive or non-linear devices such as coils, capacitors, motors,florescent bulbs (plus ballast), etc. the circuit current'samplitude/time graph is more or less different from a sine wave, whichmakes the Apparent Power's amount higher than the Real Power's amountand causes the PF parameter' value to drop accordingly.

In other words, in an AC circuit the Power Factor parameter providesinformation about how closed the circuit's current (against time)graphic shape is to its voltage's (against time) graphic shape. Simply,for a sine wave “generator—load” system, any alteration of the currentgraphic shape (including the phase) in respect to a sine wave shape,will be reflected in a lower than 1 Power Factor parameter. The lowerthe PF amount, the worse the transfer of the energy in a specificgenerator/load electrical system.

All existing electronic devices (such as computers, TV sets, monitors,stereos, industrial equipment, medical equipment, etc), require aninternal DC voltage supply, obtained by converting the AC currentavailable from the standard power line.

As FIG. 2 shows, a simple bridge rectifier and a relatively large value(100-470 uF) capacitor are typically used for this AC to DC conversion.

As FIG. 3 illustrates a Voltage Doubler AC/DC converter which can beused, when a high output DC voltage is needed, but the input rms voltageis low (i.e. 90-120 Vrms).

Since the bulk capacitor acts as a storage device, after a few cycles,the voltage across the capacitor remains at a high DC value amount,slightly lower than the pick input voltage. As a result of this storagepropriety, the capacitor re-charges periodically only for a short partof the AC cycle, when the momentary AC voltage amount exceeds thecapacitor voltage amount (the Rectifier Bridge's diodes are directpolarized) and stops charging just as the AC voltage reaches its maximumpeak value and the Rectifier Bridge's diodes start being reversedpolarized. In this situation, the circuit current shape becomes a sharppulse looking more like a triangle (see FIG. 26, B) than a sine wave andis lasting only about 2 mS from the total period of about 8.33 mS (a 60Hz sine wave generator's half cycle). The power generator provides ahalf sine wave Voltage of about 8.33 mS. However, the circuit Current'sgraph follows a 2 mS “triangle” shape and, hence, the Power Factoramount will be considerable less than 1.

Nevertheless, it is well known that all current forms (except perfectsine waves) generate an infinite number of harmonics (in computer PowerSupplies industry, the first 51 harmonics are usually considered in theA.THD calculations), that may create serious perturbations to a lot ofsensible pieces of equipments such as telecommunications devices,medical equipment and/or high precision industrial robots. This sharpcurrent pulse described above is a very dangerous noise source, whichday by day increases its power via millions of new electronic unitscoupled together to the same electrical energy bus line.

In conclusion, the repercussions of this classic rectifying processconsist in a major and unneeded increasing of the input rms current, anda hazardous generation of electrical noise, reflected in a significantdecrease of the PF parameter (down to about 0.6 typically) and increaseof the current THD (Total Harmonic Distortions) parameter (up to over120%).

Because of all these above, the electrical utilities (the high powertransformers' as well as the wiring circuit's size are calculatedproportional to the rms current's amount) must employ much moregenerating and distributing capacity, for delivering actually just moreApparent Power (which goes in heat under the provider's expenses) butnot more Real Power, which is the one used and paid by the consumers.

Similarly to the “Catalytic Converters”, that is requested now in moreand more countries for decreasing the Cars' Smog Pollution, the “PFCCircuits” must be introduced worldwide, for preventing the ElectricalNoise Pollution and the unnecessarily waste of Electrical Energy.

About two years ago Japan and the European Union authorities set severestandards for PF and THD acceptable levels, as a protection against alarge increase of low PF electrical equipment. The new standard refersto all electrical devices over 70w input power, and is going to be setfor even a lower power (50w) in future.

The existing electronic components (such as diodes, transistors, coilsetc.), do not allow us yet to reach an efficiency amount near 100%,because of the energy lost in heat. However, there are already activePFC circuits (including the one subject of the present invention), ableto increase the Power Factor coefficient, up to over 0.999 and decreasethe THD down to less than 1%.

Therefore, there is a vital need to resolve the PFC and THD issuesrapidly, economically and efficiently.

3. The Related Art

3.1 Passive PFC Solutions

The simplest methods to increase PF and lower THD are the ones usingpassive components (inductors and capacitors). Usually, the performancesof these kinds of “Passive PFC Solutions” are relatively low, just nearthe “acceptable” limits of the industry standards.

In FIG. 35B are presented the improved performances (Bench Data) of aPassive PFC 200w Computer power supply (having a 1 mH, 1.5 pounds,correction coil), in respect to the performances of the same powersupply before any correction has been done, shown in FIG. 35A. As theabove mentioned figures show, the main parameters, such as PF(increasing from 0.669 up to 0.786) and A.THD (decreasing from 98.62%down to 60.50%), do not gain a dramatic improvement after a Passive PFCcircuit has been applied.

Typically, the input current shape looks similarly to the oneillustrated in FIG. 26, C, which is self explanatory regarding thecurrent graph shape's improvement.

However, besides lower quality performances, some factors like size,weight, mechanical vibrations and self-heat of these passive components(increasing proportional to the output power) forces the designers toconcentrate active solutions in the power range exceeding 100 W.

Considerable effort has been expended over the last 15 years to developthese Active Power Factor Correction methods, targeting lower cost,better efficiency, higher power factor and lower harmonic distortions.

Until Japan and Europe start persisting on PFC and THD superiorstandards, these PFC efforts were focused mostly to the Florescent Lightfield of industry. Now, all electronic devices using “bridgerectifier/bulk capacitor” conversion system (hundreds of millions units)are considered dangerous “pollution sources” for the electricalgenerators and their related buss lines.

3.2 Active PFC Solutions

Better methods of increasing the PF and lowering the THD in a powersupply circuit are the ones comprising so called “Active PFC Systems”that include typically an oscillating coil activated by a power MOSFETtransistor (inverter circuit), which is controlled by a PFC ControllerCircuit.

The PFC Controller Circuit is basically a classic Pulse Width Modulator(PWM) circuit which includes typically, a “Multiplier” and some othermultiplier's related sub-circuits, necessarily for forcing the powersupply's input current shape to follow the input voltage's one (i.e. asine wave shape).

3.3 Pulse Width Modulation Circuits

FIG. 4 illustrates a Classic PWM Controller (UC384x series) Circuit'sOpen Loop Laboratory Fixture and the Timing Diagrams related to the highfrequency driving control pulses necessarily for controlling a powerMOSFET's invertors circuit. This very popular Current Mode PWMintegrated circuit is now build and sold in large volume by over 50major manufactures (including TI, Motorola, ST, ON Semiconductor,Fairchild, etc.), world wide. The main functional blocks of an UC384xare an internal supply and protections block (ISP), a voltage referencesblock (Vref), an output driver block (DRV), a pulse width modulationlogic block (PWM Logic), a voltage error amplifier block (VEA), avoltage limiter block (VL), a pulse width modulation Comparator block(C), and an oscillator block (OSC). Eight I/O electrodes: Comp (1), Vfb(2), Is (3), RC (4), GND (5), Output (6), Vcc (7) and REF (8) areconnecting the internal functional blocks to the controller's relatedcircuit.

The ISP block supplies and protects for over voltages all the otherinternal blocks. The Vref block provides high precision (1%) referencesvoltages to the internal and external (via REF electrode) circuit. TheDRV block is basically a high voltage (20v) buffer for the “Y” signaloutputted by the PWM Logic block.

The main purpose of attaching the PWM Logic block between the PWMComparator and DRV is to prevent more than one output pulse during oneOSC's cycle. Two examples (using NOR gates or NAND gates) of a typicalPWM Logic block schematic diagram are shown in FIG. 6 h 1 and FIG. 6 h2. The two schematics are equivalent, both functioning in accordance tothe same Truth Table shown in FIG. 6 h 3. Accordingly, this PWM Logiccircuit allows 1 (HIGH) level at its Y output, only when the R input isalready in 0 (LOW) logic and the S input turns 0 (LOW). If the R inputswitches to 0 (LOW) after the S input switches to 0 (LOW), then output Yremains 0 (LOW) until the next OSC's cycle. The output Y turns 0 (LOW)when at least one of the two inputs (R, S) turns to 1 (HIGH).

As the Timing Diagrams of FIG. 4 show, the OSC block provides the PWMLogic block with setting (Set) pulses having the frequencypre-established by a voltage ramp (VR) signal created externally by R3and C1.

The Set pulse level is 0 (LOW) during the time when R3 is charging C1(VR voltage level increases slow) and the Set pulse level is 1 (HIGH)during the time when C1 is internally discharged into the OSC block (VRvoltage level decreases faster).

Obviously, the Set pulse lasting time is proportional to C1 value (aslarge C1 value is, as longer discharge time follows).

When S reaches 0 (LOW) logic level (assuming that R is LOW already), theY output (of the PWM Logic block) switch to 1 (HIGH) logic level. The Youtput (and implicitly the main Output (6) electrode) remains at HIGHlogic level until one of the R, S inputs reaches the 1 (HIGH) logiclevel.

If the R input never switches 1 (HIGH), then the Output (6) will providea maximum duty/cycle pulse similar, but in opposite phase, to the Setsignal.

In order for R to switch 1 (HIGH) the current sense Is (3) input'svoltage amount must be higher than the fraction of the Comp (1) voltageamount delivered by the VL block (VLo) to the inverting input of thepulse width modulation comparator (C).

Typically, the Comp (1) voltage is resistively divided (⅓) and alsolimited at max 1V by the VL block, so by buffering the VR-A signalincoming from RC (4) via a NPN transistor Q1 and adjusting its levelproperly, via the potentiometer P2, a lower max duty/cycle can be set,in respect to the 1V max threshold established at the inverting input ofthe PWM comparator (C). P2 is able to adjust a max duty/cycle, at anyratio between 30% and 90% (some of the UC384x controllers' seriescircuits contain inside an extra sub-circuit for limiting the max dutycycle at 50%). If P2 is connected in series with a current senseresistor to ground, the PWM controller IC can work in a Current/Voltagemode combination, fact which provides more stability to the entirecircuit.

The minimum duty/cycle is provided by VEA when the amount of voltage atVfb (2) electrode is higher than Vref2 (2.5V+/−1%). R1, R2 and P1 areable to provide a voltage higher than 2.5V, since the REF (8) voltage is5V (+/−1%).

R4 provide VEA with feedback and stability, R5 act as a load for theOutput (6) electrode and C2, C3 are preventing high frequencyoscillations at Vcc (7) and REF (8) electrodes. By adjusting P1, theOutput pulse minimum ON time can be decrease, in voltage mode, down to1-3 uS, depending of the 384x IC manufacturer. The Timing Diagramssection of FIG. 4 shows progressively the Output pulse as a function ofthe Set, VLo, Is and R signals.

In accordance to the above description, the Output pulse starts when Setreaches its (LOW) level, and stops when Reset reaches 1, so the DRVpulse duty/cycle is proportional to the VLo signal momentary voltageamount, in respect to GND (5). If R remains LOW, then Output pulse turnsLOW when the next Set pulse arises (max duty cycle). If R remains HIGHor turns LOW after Set switches LOW, then the Output pulse remains LOW(no more Output pulses). As fast is the pulse width modulationcomparator (C), as short is the minimum ON time of the Output pulse.Unfortunately, being designed as a current mode PWM controller, theexisting 384x IC controllers series reaches, in voltage mode ofoperations (via Q1, as voltage ramp driver) a minimum Output pulse ONtime around 1 uS or more, which is a too long time for an accuratecontrol at high frequency. For a high performances PFC System, theminimum ON time pulse needed is less than 0.1 uS (preferable 0.01 uS).Several low cost solutions of resolving this 384x controllers familyinconvenient will be further presented as subjects of this invention.

FIG. 5 illustrates a complete Classic PWM Controller Circuit (UC384xseries) and the Timing Diagrams related to the control pulse outputtedto the power MOSFET's gate, in closed loop, this time, with the load'svoltage and the MOSFET current. The Output pulse ON time is limitedsimultaneously by a “too high voltage” sensed at Vfb (2) electrode(proportional to the Load Voltage) and/or a “too high current” sensed atIs (3) electrode (proportional to the L1 and M1 current). In this way, aPWM controller circuit is able to keep a constant output DC voltage,despite large variations of the input voltage and/or load's current.This PWM circuit can represent, eventually, a “core” sub circuit for a“Low Cost High Performances PFC System.”

FIG. 6 shows all necessarily Logic Symbols and Truth tables used in theRelated Art and/or Description of the Embodiments sections.

3.4 Power Factor Correction Circuits

FIG. 7 presents a High Performances PFC Circuit and Test Data. TheMC33368 is a classic ON Semiconductor's High Performances PFC ICcontroller, featuring the followings:

-   0.972>PF<0.997, 0.6%>A-THD<5.8%, 92.2%<Eff<96.8%, $/IC=1.64.

These above performances reach the highest level in the industry,however the parts count (25), the inductance of L1 (720 uH) the size andthe entire solution cost, are factors incompatible with the existinglarge volume (low cost) market.

FIG. 8 presents a Low Cost PFC Circuit and Test Data. The MC33260 is aclassic ON Semiconductor's low cost PFC IC controller, featuring thefollowings:

-   0.967>PF<0.996, 7.0%>A-THD<18.8%, 90.2%<Eff<95.7%, $/IC=0.84).

These lower performances and also the fact that MC33260 works invariable frequency mode may determine some end users to look for bettersolutions. However lower parts count (14), lower inductance of L1 (320uH) lower size and lower entire solution cost, represent the mainadvantages which made this solution very popular in the existing largevolume market.

Description of a Classic PFC Circuits

FIG. 9 illustrates the most common Active PFC System containing, besidesthe Alternative Current Generator (Vac), five functional blocks such asa Low Pass Filter (LPF), a Bridge Rectifier (BR), a Power FactorCorrection Large Signal Circuit (PFC-LSC), a Complex Load (CL) and aPower Factor Correction Small Signal Circuit (PFC-SSC), which isrepresented by the Controller Circuit and some extra parts such as Rvinand Rvout, included in the Controller Related Circuit (CRC).

The LPF block designed purpose is to protect the input generator fromthe high frequency noise incoming from the PFC-LSC block and containsusually, an input filtrating capacitor Cf1, a symmetrical double coilfilter Lf1 and a second filtrating capacitor Cf2. The BR block comprisesa bridge of four rectifying diodes (Dr1-DR4) that convert the AC inputvoltage into a pulse (semi cycles) DC voltage. The CL block contains abulk capacitor Cb and a resistive load RI. The PFC-LSC block comprisesan inductor, L1, a diode, D1, a capacitor C1, a power MOSFET transistorM1 and some times, an additional snubber circuit including a capacitorCs a resistor Rs and a diode Ds. The purpose of this attached SnubberCircuit is to decrease the M1 heat dissipation cumulated at thebeginning of it's each OFF cycle. Simply, when M1 switches OFF, itsdrain voltage increases very fast from zero up to 300-500v, because ofthe coil L1 self-inductance (reverse voltage). The capacitor Cs,appearing in parallel to M1 (via Ds), creates a necessarily delay (froma few hundred nS up to over one uS, function of Cs and L1 values) tothis voltage increasing course. This delay must be long enough for theMOSFET to switch OFF completely, or at least to reduce substantially itsdrain-source current when M1 drain electrode reaches a significant highvoltage (P=V*I). When M1 switches back ON, Cs is discharge into M1circuit via Rs, which reduces the discharge current.

This snubber circuit just decreases the MOSFET working temperature butdoes not increase the efficiency of the circuit, because the resistor Rsdissipates in heat about the same electrical energy that has beenapparently saved from the M1's OFF switching transit time. The onlyadvantage for attaching this circuit is a lower sized aluminum heat sinkand/or a lower working temperature for M1.

A novel, low cost, solution for a high efficiency snubber circuit willbe presented as a further subject of this invention.

Two input terminals, “Vin+” and “Vin−”, connect the PFC-LSC block to BRand another two output terminals “Vo+”, and “Vo−”, to the CL block.

The PFC-SSC includes itself a Multiplier (MULT) block, a Current ErrorAmplifier (CEA) block, Voltage Error Amplifier (VEA) block, a PWMComparator (PWMC) block, a PWM Logic block, an oscillator (OSC) blockand a Driver (DRV) block.

As an important observation, except the Multiplier sub-circuit, all theother functional block of a typical PFC controller are also included inthe low cost PWM controller (i.e. 384x IC series).

Five I/O electrodes such as Vins (sensing the Vin+ momentary value), Is(sensing the M1 momentary current), DRV (providing the ON/OFF switchingcontrol to the gate of M1), Vfb (sensing the “Vo+” momentary amount) andGND are necessarily in order for PFC-SSC to be able to control thePFC-LSC block.

When the voltage outputted by Vac is applied to the PFC-LSC through theLPF and BR blocks, the full-wave rectified pulse outputted by BR appearsat Vin+ and Vin− (positive polarity at Vin+).

Initially at “Vo+” (in respect to GND) a DC voltage is created, inamount slightly lower than the peak input voltage and the input currentshape is similarly to the one shown in FIG. 26, B.

The PFC-SSC block provides the MOSFET's gate with a relatively highfrequency (30-200 KHz) square wave pulse. M1 remains ON until thecurrent in L1 reaches a specific amount, then by switching OFF; theenergy stored in L is delivered to CL, through D1.

As soon Cb is charged up to a higher value than the peak of Vin (boostconverter), there is no more direct current between Vac and CL (BRdiodes and D1 are reverse polarized) so the input current shape dependsof the L1 average current only, which is controlled in switching way bythe Controller Circuit via M1.

The Multiplier block “MULT” is designed to control the MOSFET pulse insuch a way (by multiplying the VEA signal in a specific ratio, functionof “Vin+” level) that the momentary current value in L1 (via M1 circuitto GND) becomes proportional to the momentary AC generator voltageamount.

That forces the input current shape to follow the input voltage shape,fact which pushes the PF parameter level near 1. The final input currentshape may have any form between the ones illustrates in FIG. 26D andFIG. 26E, which means a PF parameter from about 0.9 to 0.999.

Cost vs. Performances

For the “Large Volume” (a few millions units/month) power suppliesmarket (such as Computers, Display Monitors, orPrinters/Scanner/Fax/Copier units), the cost price is the mandatorycondition for a new circuit's design and execution's decision.

A $0.10/unit minimum saving, without altering the initial performances,is a significant challenge for the worldwide power supplies designers.All PFC controller circuits include, besides a PWM sub-circuits, a fewextra functional blocks (most typical a Multiplier circuit), that ofcourse increase the controller total cost, in accordance to the attachedsub-circuits complexity.

A classic high performances PWM IC controller (such as UC384x) thatincludes, except the multiplier, almost all the other necessarilyfunctional blocks of a PFC controller IC, costs just about $0.27/IC.

However, the above classic PFC solutions provide high performances withMC33368 at $1.60/IC, or good (or reasonable) performances with MC33260at $0.84/IC.

Therefore, a need exists for a Low Cost High Performances Power FactorCorrection Circuit which is reliable, efficient, low sized, simple indesign, includes less parts count and does not require a sophisticatedand expensive Multiplier sub-circuit.

SUMMARY OF THE INVENTION

Brief Summary

Accordingly, the present invention is directed to a “non-multiplier” LowCost High Performances Power Factor Correction Circuit, including novelmethods, systems and apparatuses, that substantially reduce one or moreof the problems due to limitations and disadvantages of the relatedand/or prior art.

These related art circuit's limitations and/or disadvantages can besensed in one or more of their technical and economical feature such as:Power Factor, Total Harmonic Distortions (THD), Efficiency (Eff),Controller IC's Performances vs. Cost, Simplicity in Design andImplementation, Circuit's Parts Count (CPC), size, weight, workingtemperature, Entire Circuit's Cost, etc.

A high PF is needed; the closer this parameter is to unity or 1, thelower the loss in heat in an AC Generator Wiring Systems and moreconsumers can be connected to the same AC Buss Line.

A low THD is requested; the lower the value of this parameter, the lowerthe electrical noise introduced by each Complex Load System (such ascomputers, monitors, printers, copiers, TV sets, etc) back into the ACBus Line.

A high Eff. is important, the closer this parameter is to 100%, the lessun-needed heat (because of the electrical devices' dissipation) attachedto computers, monitors or any other electronic units, is included in theconsumers' monthly electrical bill.

The Controller IC's Performances reflects the value of the entire PFCCircuit, however its cost depends of its internal complexity and pinscount (typically 8, 14 or 16 pin standard packaging). For about $1/unitthe 8 pin IC configurations, having less than 15 extra parts included inthe related circuit, are now the most appreciated PFC IC Controllers.

The Simplicity in Design and Implementation aspect is important forgiving equal chances of production to large and small manufacturers, forup grading their existing products. In other words, the best novelproduct is not the one which has fantastic performances, however eachnew specific custom design requests a few months of computer simulationsplus bench prototyping process and more than that, only 2 or 3 Hi-Techmanufactures (in the entire world) are capable to provide the maincircuit's components or sub-ensembles.

A low CPC is essential for decreasing the unit production cost (i.e.fewer devices in the assembling, soldering and testing process) and forincreasing the reliability of the entire circuit (less parts—lowerfailures chances).

Lower size and weight are essential features not only for end users'advantages but also for significant worldwide transportation's costsavings.

Lower working temperature means better safety and reliability, less sizeand in some situations a significant cost savings, since most of low (orreasonable) cost parts' ambient working temperature is limited to amaximum of 70*C. Over this temperature threshold, most of the electronicparts' (such as Integrated Circuits, transistors, resistors, capacitors,diodes and coils' cores) may double their cost.

The reduction of the Entire Circuit's Cost is an imperative, becausethese PFC circuits will be introduced (sooner or later) in all powersupplies that may represent a threat (P>50w) for the safety of theelectrical buss lines and the production of such power supplies exceedsalready one hundred million units/year, worldwide. A lower cost/circuitcan be achieved by decreasing the parts count and/or the size of theinductor and/or the MOSFET's aluminum heat sink and/or the workingtemperature and/or the Controller IC complexity, without altering thecircuit's performances.

One of the objectives of this Patent Application is to provide a LowCost High Performances Power Factor Correction Circuit, all the aboveitems represent other object of the present invention novel circuits'target features.

The following table presents comparatively, a part of the abovediscussed PFC circuits' features of two worldwide much appreciated PFCdevices such as MC33260, and MC33368, versus the present invention'sApparatus prototype's Bench Data (NEWCTRL). A.THD Cost/unit PerformancePFC PF (%) Eff. (%) IC Acceptable Passive 0.786 60.5 97.5% — GoodMC33260 0.975- 7.00-16.5 90.2-94.5 $0.84 0.996 High MC33368 0.983-0.70-5.80 92.2-95.7 $1.60 0.997 High NEWCTRL 0.998- 0.88-4.00 92.2-96.6$0.40 0.999

Obviously, the NEWCTRL, further subject of the present invention,provides better performance as a classic high quality PFC controllercircuit (MC33368), for just 25% of the cost/unit IC.

In order to demonstrate these above “NEWCTRL” high performances underlow cost, several Large Signal Circuit embodiments and also severalSmall Signal Circuit embodiments will be further fully described, assystems, sub-systems or sub-circuits of a Low Cost High PerformancesPower Factor Correction System, the main subject of the presentinvention.

OBJECTS OF THE INVENTION

It is an object of the present invention to provide a new method ofimproving near unity the Power Factor parameter, not by using aMultiplier sub-circuit included in the main controller system, but bythe means of a Constant Pulse Proportional Current (CPPC) ControlMethod, which forces the input current graphic form to follow the inputvoltage shape, (i.e. sine-wave) in an AC Generator—Complex Load System.

t is another object of the present invention to provide a near unityPower Factor Correction Boost Converter System, able to perform inaccordance to the CPPC Control Method and procedure.

It is still an object of the present invention to provide a near unityPower Factor Correction Buck-Boost Converter System, able to perform inaccordance to the CPPC Control Method and procedure.

It is still another object of the present invention to provide a nearunity Power Factor Correction High Efficiency Snubber (HES) BoostConverter System, able to perform by following the CPPC Control Methodand being also compatible with the classic way (i.e. the Multipliermethod) of control.

It is yet an object of the present invention to provide a near unityPower Factor Correction Voltage Doubler (VD) Boost Converter System,able to perform by following the CPPC Control Method and being alsocompatible with the classic way (i.e. the Multiplier method) of control.

It is yet another object of the present invention to provide a nearunity PFC Controller System (NEWCTRL) having novel functional blocksand/or a novel system's architecture, in order to perform in accordanceto the CPPC Control Method and procedure.

It is also an object of the present invention to provide a StartEnforcement (SE) functional block sub-circuit(s) able to perform inaccordance to the CPPC Control Method and being also compatible with theclassic way (i.e. the Multiplier method) of control.

It is also another object of the present invention to provide a NonLinearity Correction (NLC) functional block sub-circuit(s), able toperform in accordance to the CPPC Control Method and procedure.

It is another object of the present invention to provide an Analog ResetMethod (ARM) able to perform in accordance to the CPPC Control Methodand also able to improve the analog-logic data transfer in a classicMixed-Signal circuit.

It is still an object of the present invention to provide an AnalogReset Comparator (ARC) functional block sub-circuit(s), able to performin accordance to the Analog Reset Method.

It is still another object of the present invention to provide an AnalogReset Oscillator (AR-OSC) functional block sub-circuit(s), able toperform in accordance to the Analog Reset Method.

It is yet an object of the present invention to provide an Analog ResetPulse Width Modulator Logic (AR-PWM Logic) functional blocksub-circuit(s), able to perform in accordance to the Analog ResetMethod.

It is yet another object of the present invention to provide an AnalogReset Voltage Ramp Driver (AR-VRD) functional block sub-circuit(s), ableto perform in accordance to the Analog Reset Method.

It is also an object of the present invention to provide an Analog ResetSystem (ARS) circuit(s), able to perform in accordance to the AnalogReset Method.

It is also another object of the present invention to provide an AnalogReset Pulse Width Modulation (ARS-PWM) Hybrid Controller circuit(s),able to perform in accordance to the Analog Reset Method.

It is still an object of the present invention to provide a Power FactorControl Apparatus circuit, able to reach very high performances by usingthe Constant Pulse Proportional Current Method and the Analog ResetMethod.

To achieve these and other advantages, and in accordance with thepurpose of the present invention, as embodied and broadly describedherein, the present invention is a Low Cost Power Factor CorrectionSystem which generically includes an alternative current voltagegenerator (Vac), a low frequency pass filter sub-circuit (LPF), a fourdiodes bridge rectifier sub-circuit (BR), a power factor correctionlarge signal sub-circuit (PFC-LSC), a power factor correction smallsignal sub-circuit (PFC-SSC) and a complex load sub-circuit (CL).

The invention consists in the novel parts, constructions, arrangements,combinations and improvements herein shown and described. Theabove-stated and other objects and advantages of the invention willbecome apparent from the following description when taken with theaccompanying drawings. It will be understood, however, that the drawingsare for purposes of illustration and are not to be construed as definingthe scope or limits of the invention, reference being had for the latterpurpose to the claims appended hereto.

Additional objects, features, and advantages of the invention will beset forth in the description that follows, and in part will be apparentfrom the description, or may be learned by practice or computersimulations of the circuits presented as subject of this invention. Theobjective and other advantages of the invention will be realized andattained by the apparatus and methods particularly pointed out in thewritten description and claims hereof, as well as the appended drawings.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention as claimed.

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification. In addition, the accompanying drawingsillustrate the embodiments of the invention and, together with thedescription, serve to explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and features of the present invention willbecome apparent to those ordinarily skilled in the art upon review ofthe following description of specific embodiments of the invention inconjunction with the accompanying figures, wherein:

Related Art

FIG. 1 is a classic Resistive Load Classic AD/DC Converter Circuitincluding an AC generator Vac, a full-wave rectifier bridges BR and aload resistor, Rload;

FIG. 2 is a classic Reactive Load Classic AD/DC Converter Circuitincluding an AC generator Vac, a full-wave rectifier bridge BR, a loadresistor Rload and a bulk capacitor Cb across to the load resistor;

FIG. 3 is a classic Voltage Doubler AC/DC Converter Circuit including anAC generator Vac a full-wave rectifier bridge BR, a load resistor Rloadand two bulk capacitors Cb1, Cb2;

FIG. 4 is an UC384x—Open Loop Laboratory Fixture Circuit and TimingDiagrams presentation;

FIG. 5 is a Classic PWM Controller Circuit and Timing Diagrams,presenting the UC384x series Controller Circuits in a typical closedloop system;

FIG. 6A-H is a generic presentation of standard Symbols and Truth Tablesused in the Mixed Signal Circuits' design;

FIG. 7 is a typical High Performances PFC Circuit and Test Data,presenting the MC33368 Controller Circuit;

FIG. 8 is a typical Low Cost PFC Circuit and Test Data, presenting theMC33260 Controller Circuit;

FIG. 9 is a Classic Power Factor Correction Circuit including an ACgenerator Vac, a full-wave rectifier bridge BR, a Large Signal CircuitPFC-LSC, a Small Signal Circuit PFC-SSC and a Complex Load Circuit CL;

Embodiments

FIG. 10 is a Low Cost High Performances Power Factor Correction System(LCHPPFCS) schematic diagram, presenting the Boost Constant PulseProportional Current PFC Inverter Circuit's (CPPC PCF-IC) embodiment;

FIG. 11 is a LCHPPFCS schematic diagram, presenting the Buck-Boost CPPCPCF-IC embodiment;

FIG. 12 is a LCHPPFCS schematic diagram, presenting the High EfficiencySnubber-Boost CPPC PCF-IC embodiment;

FIG. 13 is a LCHPPFCS schematic diagram, presenting the VoltageDoubler-Boost CPPC PCF-IC embodiment;

FIG. 14 is a Generic-Boost CPPC PCF-IC embodiment, including a selfsupply circuit for the controller circuit;

FIG. 15 is a generic schematic diagram embodiment for the Constant PulseProportional Current Power Factor Correction Small Signal Circuitincluding the CPPC PFC Controller Circuit (NEWCTRL) including 13functional blocks such as the Internal Supply and Protection (ISP),Driver (DR), Current Limiter (CL), Voltage References (Vref), AnalogReset Pulse Width Modulation Logic (AR-PWM Logic), Analog ResetOscillator (AR-OSC), Soft Start (SS), Non Linearity Correction (NLC),Analog Reset Voltage Ramp Driver (AR-VRD), Voltage Error Amplifier(VEA), Voltage Limiter (VL), Analog Reset Comparator (ARC), StartEnforcer (SE) and a minimum parts Controller Related Circuit;

FIG. 16 is a NEWCTRL sub-circuit's schematic diagram embodimentincluding its ISP, DR, CL, and Vref functional blocks;

FIG. 17 is a NEWCTRL sub-circuit's schematic diagram embodimentincluding its SS, NLC, VEA, VL″ and SE functional blocks;

FIG. 18A-C is a NEWCTRL sub-circuit's schematic diagram including a2^(nd), 3^(rd) and 4^(th) embodiment versions of its “NLC” functionalblock;

FIG. 19A-E is a NEWCTRL sub-circuit's schematic diagram including a1^(st), 2^(nd), 3^(rd) and 4^(th) embodiment versions of its “ARS-PWM”circuit including the AR-OSC, AR-VRD, ARC and AR-PWM functional blocks,versus a classic PWM circuit;

FIG. 20A-D is a NEWCTRL sub-circuit's schematic diagram including a1^(st), 2^(nd) and 3^(rd) embodiment versions of its “AR-OSC” functionalblock and the related Timing Diagrams;

FIG. 21A-B is a NEWCTRL sub-circuit's schematic diagram including a1^(st) and 2^(nd) embodiment versions of its “AR-VRD” functional block;

FIG. 22A-B is a NEWCTRL sub-circuit's schematic diagram including a1^(st) and a 2^(nd) embodiment versions of its ARC functional block;

FIG. 23A-B is a NEWCTRL sub-circuit's schematic diagram including a1^(st) and 2nd embodiment versions of the AR-PWM Logic” functionalblock;

FIG. 24A-C is a NEWCTRL sub-circuit's schematic diagram including a1^(st), 2^(nd) and 3^(rd) embodiment versions of an Analog Reset SystemPWM Hybrid Controller Circuit;

FIG. 25 is a LCHPPFCS Apparatus Embodiment's schematic diagram;

Timing Diagrams

FIG. 26A-E is a graphic representation for the Vac Generator Voltage andCurrent Timing Diagrams for resistive and/or complex load circuits;

FIG. 27A-G is a graphic representation for the MOSFET's Voltage andCurrent Timing Diagrams in a CPPC Boost circuit vs. CPPC HES-Boostcircuit;

FIG. 28A-E is a graphic representation for the Classic PWM vs. ARS PWMCircuit's Voltage Timing Diagrams;

Design and Implementation

FIG. 29A is a generic presentation of two schematic diagrams, subject ofa simultaneous computer simulation design, for an accurate comparison(by using the same program and “Spice Model” parts and then overlappingthe results and/or Timing Diagrams) between a Classic AC/DC Converter(1) vs. a Boost CPPC PFC System (2);

FIG. 29B is a chart including General Specifications, Parts List andsimulation results for the schematic diagrams illustrated in FIG. 29A;

FIG. 29C-H reveal the simulation results, by presenting six significant“time spots” (2 spots/page) of the FIG. 29A circuits;

FIG. 30A is a generic presentation of two schematic diagrams, subject ofa simultaneous computer simulation design, for an accurate comparison(by using the same program and “Spice Model” parts and then overlappingthe results and/or Timing Diagrams) between a Boost CPPC PFC System (1)vs. a Buck-Boost CPPC PFC System (2);

FIG. 30B is a chart including General Specifications, Parts List andsimulation results for the schematic diagrams illustrated in FIG. 30A;

FIG. 30C-H reveal the simulation results, by presenting comparativelysix significant “time spots” (2 spots/page) of the FIG. 30A circuits;

FIG. 31A is a generic presentation of two schematic diagrams, subject ofa simultaneous computer simulation design, for an accurate comparison(by using the same program and “Spice Model” parts and then overlappingthe results and/or Timing Diagrams) between a Boost CPPC PFC System (1)vs. a HES-Boost CPPC PFC System (2);

FIG. 31B is a chart including General Specifications, Parts List andsimulation results for the schematic diagrams illustrated in FIG. 31A;

FIG. 31C-J reveal the simulation results, by presenting comparativelyeight significant “time spots” (2 spots/page) of the FIG. 31A circuits;

FIG. 32A is a generic presentation of two schematic diagrams, subject ofa simultaneous computer simulation design, for an accurate comparison(by using the same program and “Spice Model” parts and then overlappingthe results and/or Timing Diagrams) between a Boost CPPC PFC System (1)vs. a Voltage Doubler-Boost CPPC PFC System (2);

FIG. 32B is a chart including General Specifications, Parts List andsimulation results for the schematic diagrams illustrated in FIG. 32A;

FIG. 32C-H reveal the simulation results, by presenting comparativelyeight significant “time spots” (2 spots/page) for the FIG. 32A circuits;

FIG. 33A is a generic presentation of two schematic diagrams, subject ofa simultaneous computer simulation design, for an accurate comparison(by using the same program and “Spice Model” parts and then overlappingthe results and/or Timing Diagrams) between a Classic PWM circuit (A)and a ARS-PWM circuit (B);

FIG. 33B is a chart including General Specifications, Parts List andsimulation results for the schematic diagrams illustrated in FIG. 33A;

FIG. 33C-H reveal the simulation results, by presenting comparativelysix significant “time spots” (2 spots/page) of the FIG. 33A circuits;

FIG. 34A is a generic presentation of an Analog Reset Oscillatorschematic diagram designed (by computer simulation's means) for a benchapparatus prototype;

FIG. 34B is a chart including General Specifications and Parts List forthe schematic diagram illustrated in FIG. 34A;

FIG. 34C-D reveals the simulation results, by presenting two significant“time spots” of the FIG. 34A circuit;

Bench Test Data

FIG. 35A is a Test Data printout sheet referred to a No PFC—Classic 200wComputer Power Supply unit;

FIG. 35B is a Test Data printout sheet referred to a Passive PFC (1 mHcoil) applied to the same Power Supply presented in FIG. 35A;

FIG. 36A is a 160w LCHPPFCS Bench Prototype Apparatus' SchematicDiagram, designed for a Test Data performances' evaluation of theEmbodiment presented in FIG. 25;

FIG. 36B is the Parts List for the schematic diagrams illustrated inFIG. 36A;

FIG. 37A is a 90Vac (input)Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a 160w LCHPPFCS Bench Prototype in its1^(st) comparison stage respectively: no DC supply to the NEWCTRLcircuit (no PFC);

FIG. 37B is a 90Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its2^(nd) comparison stage respectively: Open Loop NEWCTRL's FB circuit;

FIG. 37C is a 90Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its3^(rd) comparison stage respectively: no NLC included in the NEWCTRLcircuit;

FIG. 37D is a 90Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its4^(th) comparison stage respectively: Full Exploitation of the NEWCTRLsub-circuits;

FIG. 38A is a 120Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a 160w LCHPPFCS Bench Prototype in its1^(st) comparison stage respectively: no DC supply to the NEWCTRLcircuit (no PFC);

FIG. 38B is a 120Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its2^(nd) comparison stage respectively: Open Loop NEWCTRL's FB circuit;

FIG. 38C is a 120Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its3^(rd) comparison stage respectively: no NLC included in the NEWCTRLcircuit;

FIG. 38D is a 120Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its4^(th) comparison stage respectively: Full Exploitation of the NEWCTRLsub-circuits;

FIG. 39A is a 240Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a 160w LCHPPFCS Bench Prototype in its1^(st) comparison stage respectively: no DC supply to the NEWCTRLcircuit (no PFC);

FIG. 39B is a 240Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its2^(nd) comparison stage respectively: Open Loop NEWCTRL's FB circuit;

FIG. 39C is a 240Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its3^(rd) comparison stage respectively: no NLC included in the NEWCTRLcircuit;

FIG. 39D is a 240Vac (input) Test Data Printout Sheet (performed usingVoltech PM100 Power Analyzer) for a LCHPPFCS Bench Prototype in its4^(th) comparison stage respectively: Full Exploitation of the NEWCTRLsub-circuits; and

FIG. 40 is a complete chart illustrating the reference numbers, as wellas a succinct description, of all functional blocks, sub-circuits and/orparts included in the present patent application.

SYNOPSIS AND REFERENCES OF THE INVENTION

This chapter provides a generic guide line of the present patentapplication drawings description's order and references numbers, inrespect to its main and/or final objectives.

Accordingly, a Low Cost High Performances Power Factor CorrectionSystem—LCHPPFCS (1) is provided, as the main and final objective of thepresent invention.

The LCHPPFCS (1) comprises a Power Factor Correction Large SignalCircuit PFC LSC (2) and a Power Factor Correction Small Signal CircuitPFC SSC (3). Two different methods, a Constant Pulse ProportionalCurrent (CPPC) Method and an Analog Reset System (ARS) Method, areapplied to different sub-circuits of the LCHPPFCS (1).

The PFC LSC (2) comprises typically an alternative current voltagegenerator Vac (10) block, a low (frequency) pass filter LPF (20) block,a bridge rectifier BR (30) block, a complex load CL (40) block and, asan important subject of this invention, a Constant Pulse ProportionalCurrent Power Factor Correction Inverter Circuit CPPC PFC-IC (50) block,which may appear in different architecture versions, such as Boost,Buck-Boost, HES-Boost or VD-Boost.

The PFC SSC (3) comprises a Constant Pulse Proportional CurrentController Circuit CPPC PCF-CC (100) or simply NEWCTRL (100) and aController Related Circuit CRC (110). The NEWCTRL (100) comprises thefollowing functional blocks: ISP (150), DR (200), Vref (250), CL (350),SS (450), NLC (500), VEA (600), VL (650), and SE (750) plus an AnalogReset PWM circuit, including AR-OSC (400), AR-VRD (550), ARC (700) andAR-PWM Logic (300).

A classic PWM circuit (no ARS) comprises the same four blocks, withdifferent reference numbers: OSC (445), VRD (595), C (745) and PWM Logic(345). Because in an AR-PWM circuit only one or two blocks need to bemodified for accomplishing an ARS-PWM circuit, each version of theNEWCTRL (100) may have a different combination of Classic PWM blocks andAR PWM blocks reference numbers.

The ARS-PWM (800) Hybrid Controller includes an UC3842 (830) currentmode PWM controller integrated circuit device, together with few otherdiscrete parts, for achieving the Analog Reset Method's implementation.

The UC3842 (830) IC comprises itself, the following 9 functional blocks:ISP, DR, Vref, PWM Logic, OSC, VEA, C and VL.

Therefore, the NEWCTRL (100) final circuit version (apparatus) mayinclude just 5 functional blocks such as: an ARS-PWM (800) Hybrid PWMcontroller circuit block, an SS (450) block, an NLC (500) block, a VRD(595) block, and an SE (750) block.

The CRC (110) comprises only the low power parts connected to theNEWCTRL (100) including (in some applications) the controller's supplycircuit CSC (90).

Accordingly, were possible, reference will be made using the same numberfor a functional block or a discreet part as long that item performsexactly the same function in the LCHPPFCC (1). However, in somesituations, two different reference numbers could be used for apparentlythe same item, in order to avoid possible confusions that may occurand/or for providing an easier identifiable “set of numbers” (i.e.150-199, 200-249, etc.) to each functional block or group of discreetparts, included in the same schematic diagram.

For a proper and complete presentation of the present invention'ssubjects, in respect to the Related Art's PFC circuits' “Performancesvs. Cost” features (main subject of the present LCHPPFCS patentapplication), besides the Embodiments' full description, a complete setof “Design and Implementation” and “Apparatus Bench Prototypes' TestData figures (fully described), have been attached.

The entire present invention embodiment circuits' performances have beenmeticulously double checked at the prototype level. If for any reasons,the computer simulations results are not considered sufficientlyaccurate, a working bench prototype is immediately available uponrequest, for supporting any of the statements and/or claims furtherstipulated in this patent application.

Also, a complete Reference Numbers Chart, including a brief descriptionof each item described in this patent application, is attached in FIG.40.

The LCHPPFS Embodiments

In accordance to the present invention, a Low Cost High PerformancesPower Factor Correction System (LCHPPFCS) is provided, as main subjectof this invention, comprising a Power Factor Correction Large SignalCircuit (PFC-LSC) and a Power Factor Correction Small Signal Circuit(PFC-SSC).

The PFC-LSC comprises, typically an alternative current Voltagegenerator (Vac), a Low (frequency) Pass Filter block (LPF), a BridgeRectifier block (BR), a Complex Load block (CL), and four differentembodiment versions of a Power Factor Correction Inverter Circuit block(PFC-IC).

The PFC-SSC comprises, a Power Factor Correction Controller Circuitblock (PFC-CC) and a Controller Related Circuit (CRC).

A Constant Pulse Proportional Current—Power Factor Correction Method isapplied to the PCF Inverter of the Large Signal Circuit section andtherefore the prefix “CPPC” will be attached in the further descriptionsof all “PFC-IC” sub-circuits.

An Analog Reset System—Pulse Width Modulation Method is applied to thePWM sub-circuit of the “PFC-CC” section and therefore the prefix ARand/or ARS is attached to all blocks and/or sub-circuits that aresubjects to the implementation of this method.

For an easier presentation of several embodiment versions, the PCF LSCsection and the PFC SSC section will be separate described and finally,the entire LCHPPFCS, as main subject of this invention, will be fullydescribed in an apparatus embodiment.

In accordance to the CPPC Method, a simple Constant (frequency,duty/cycle and amplitude) Pulse square wave generator will represent thePFC SSC section, in the PCF LSC embodiments' description and vice versa,a generic boost PCF LSC will be used, as a complementary sub-circuit,for the presentation of the PFC SSC section, when a complex CPPC PCFcontroller circuit will replace the square wave generator.

Consistently, all the devices, blocks and/or sub-circuits that will befurther described in this patent application, concur in the finalachievement of a Low Cost High Performances Power Factor CorrectionSystem solution, as main subject of this invention.

Nevertheless, it is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory only and are not restrictive of the invention as claimed.

Like reference numbers and designations in the various drawings refer tolike elements.

DESCRIPTIONS OF THE LSC EMBODIMENTS

The Boost CPPC PFC—Inverter Circuit Embodiment

10.1 General Description

FIG. 10 illustrates, in accordance with the present invention, a LowCost High Performances Power Factor Correction System—LCHPPFCS (1),comprising a Power Factor Correction Large Signal Circuit PFC-LSC (2)and a Power Factor Correction Small Signal Circuit PFC-SSC (3).

The PFC-LSC (2) comprises, typically an alternative current Voltagegenerator Vac (10), a Low (frequency) Pass Filter block LPF (20), aBridge Rectifier block BR, (30) a Complex Load block CL (40), and aboost Constant Pulse Proportional Current Power Factor CorrectionInverter Circuit block CPPC PFC-IC (50).

The PFC-SSC (3) comprises, typically a Constant Pulse ProportionalCurrent Controller Circuit CPPC CC (100) and a Controller RelatedCircuit (110), however in this specific embodiment, it consists in justa “Constant (frequency, duty/cycle and amplitude) Pulse” square wavegenerator. For the reminder of this description the particularly subcircuit presented as CPPC PFC-CC (100) may be referred to as NEWCTRL(100) as a further subject of the present invention and importantsub-circuit of the LCHPPFCS (1).

The following description refers mainly to the implementation of a CPPCPFC Method into a LCHPPFCS (1) which requests in the LSC section, aboost CPPC PFC-IC (50) block and in the SSC section, a Constant(frequency, duty/cycle and amplitude) Pulse square wave generatorNEWCTRL (100).

For the remainder of this description, the particularly sub-circuitpresented as CPPC PFC-IC (50) block, may be referred to as a Boost CPPCPFC-IC (50), as a subject of the present invention and importantsub-circuit of this LCHPPFCS (1) embodiment version

Other embodiment versions for the LSC section as well as for the SSCsection will be further described, in the next chapters of the presentinvention.

10.2 The Boost CPPC PFC LSC Embodiment

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 10 a LCHPPFCS (1)Embodiment is provided, comprising a PFC-LSC (2) and a PFC-SSC (3).

The PFC-LSC (2) includes, in this embodiment's version, an alternativecurrent Voltage generator Vac (10), a Low (frequency) Pass Filter blockLPF (20), a Bridge Rectifier block BR (30), a Complex Load block CL (40)and a Boost CPPC PFC-IC (50).

The PFC-SSC (3) includes, in this embodiment's version, just a constantfrequency-constant duty/cycle square wave's generator, as arepresentation of a new CPPC PCF Controller Circuit—NEWCTRL (100). TheVac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms) sinewave voltage generators which provides a full rectified AC voltage toCPPC PFC-LSC (50), trough the LPF (20), comprising two filtratingcapacitor Cf1 (21) and Cf2 (23) flanking a symmetrical double coil Lf1(22) and also trough the BR (30), comprising four rectifier diodes DR1(31), DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to a bulk(100-470 uF) capacitor Cb (42), is supplied by (and/or trough) the BoostCPPC PFC-IC (50) block. The PFC SSC (3) comprises the NEWCTRL (100)which, in this embodiment, is just a simple high frequency (30-500 KHz)low voltage (12-20V) square wave generator, providing a “Constant Pulse”in amplitude, frequency and duty cycle.

The Boost CPPC PFC-IC (50), as embodied herein, is a complex functionalblock having two input power electrodes Vin+ (51), Vin− (52), two outputpower electrodes Vo− (53), Vo+ (54) and a control electrode DRVin (58).

The figures suggest that the Boost CPPC PFC-IC (50) improves the powerfactor in this circuit and the positions of the various terminals denotethe function of each of them. In other words, in a CPPC PFC-IC (50)schematic diagram, the internal architecture and the positions of theterminals will illustrate, alone, the particular function of eachterminal.

Internally, the Boost CPPC PFC-IC (50) block, as embodied herein,contains a two terminals oscillating coil L1 (61), a high frequency(30-500 kHz) fast rectifier diode D1 (62), a high power high frequency(30-500 kHz) MOSFET transistor M1 (63) and a capacitor CVin (64).

The coil L1 (61) has one terminal coupled to Vin+ (51) and the other onecoupled to the anode of D1 (62). The cathode of D1 (62) is coupled toVo+ (54). M1 (63) has its drain electrode coupled to the anode of D1(62), its source electrode to Vin− (52) and its gate electrode coupledto DRVin (58). CVin (64) is coupled across Vin+ (51) and Vin− (52). Vin−(52) is coupled to Vo− (53) and is also coupled to the system's groundGND (60).

The BR (30) has its AC input coupled to the LPF (20) output, itspositive output coupled to Vin+ (51) and its negative output to Vin−(52).

The CL (40) is coupled across the two output electrodes, Vo+ (54) andVo− (53).

The NEWCTRL(100) is coupled to DRVin (58) in respect to GND (60) via twoPFC SSC (3) electrodes, respectively DRV (107) and GND (105).

The Boost CPPC PFC-IC (50) block and the NEWCTRL (100), as embodiedherein, act together as the LCHPPFCS (1) specific sub-circuits, able toimprove near unity (PF>0.99) the power factor in a circuit, by the meansof an internal Constant Pulse Proportional Current Control Method, whichforces the current waveform shape to follow the voltage waveform shape,in an electrical AC Generator—Complex Load Circuit.

As further embodied herein, when a voltage is applied to the Boost CPPCPFC-IC (50) having the positive polarity at Vin+ (51) and the negativepolarity at Vin− (52) and M1 (63) is OFF, a DC voltage is created acrossthe complex load CL (40), respectively across Vo+ (54) and Vo− (53), inan amount slightly lower than the peak input voltage (classic BridgeRectifier—Bulk Capacitor AC/DC converter). As has been explained in theRelated Art section, initially the Vac (10) current shape in thiscircuit is similarly to the one shown in FIG. 26B and therefore thesystem Power Factor parameter is about 0.65 or less.

When NEWCTRL (100) starts commuting M1 (63) ON/OFF with a high frequency(30-500 kHZ), the DC voltage level across Vo+ (54)-Vo− (53) willincrease to a higher amount than the input peak voltage, because of theelectrical energy stored periodically by L1 (61) during the ON time ofM1 (63) and delivered periodically, via D1 (62) to CL (40), during theOFF time of M1 63). The value of CVin (64) is too small to alter thesystem's power factor, but large enough (100-220 nF) for protecting BR(30) for reverse high frequency oscillations.

As soon Cb (42) is charged up to a higher value than the input peakvoltage, there is no more direct current between Vac (10) and CL (40),because BR (30) and D1 (62) are reverse polarized. Starting from thismoment, the circuit's input current shape depends of the L1 (61)circuit's current only.

In other words, the Vac (10) does not “feel” anymore in its circuit thebulk capacitor Cb (42), which is the only one device able to reducesubstantially the entire circuit's power factor.

If the charging/discharging time is constant in frequency and duty/cycleand the ON time is short (and/or OFF time is long) enough for keepingthe coil L1 (61) within its linear range (in other words to prevent thecoil's core saturation), then the L1 (61) circuit's current is directproportional to the amount of its supply voltage.

Since the voltage inputted at Vin+ (51) is a full rectified sine wave,the L1 (61) circuit's momentary current's value must follow a rectifiedsine wave's shape.

Therefore, as soon the output voltage is higher (preferable 1.5-2 times)than the input peak voltage, the Vac (10) current shape changesimmediately to a form similarly to the one illustrated in FIG. 26E(almost a sine wave) without a need for a sophisticated classic“Multiplier” to be involved in the controller circuit.

If the NEWCTRL (100) frequency and duty/cycle are properly set (see FIG.27A 1-4), in respect to the L1 (61) inductance, max Vin+ and the maxload current, then the M1 drain voltage shape could be any of the onesillustrated in FIG. 27B 1-4 and the M1 drain current shape could be anyof the ones illustrated in FIG. 27C 1-4 (discontinuous mode ofoperation).

However, if the NEWCTRL (100) frequency and duty/cycle are not properlyset (i.e. OFF time to short and/or ON time too long—see FIG. 27A 5), inrespect to the L1 (61) inductance, max Vin and the max load current,then the M1 drain's voltage shape could be the one illustrated in FIG.27B 5 and the M1 drain current shape could be the one illustrated inFIG. 27C 5 (continuous mode of operation).

For a high Power Factor parameter (i.e. PF>0.99) the mode of operationsmust remain unchanged during, at least one Vac (10) semi-cycle.

10.3 Design and Implementation

The implementation of the Constant Pulse Proportional Current PowerFactor Correction method in a boost inverter circuit is much simple thanany other related art methods (especially the ones involving aMultiplier), providing considerable flexibility in design and partsselection. The PFC LSC can be as simple as a classic boost converter,under the condition of keeping a specific “Constant Pulse” in respect toeach “coil/load/control frequency” system.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, working temperature and even cost price, before the decision ofbuilding a bench prototype is taken.

By having the opportunity to simulate an Open Loop circuit (no P-Spicecontroller model, but just a simple generator providing to the MOSFET a“Constant Pulse”), the proper frequency and the max duty/cycle (i.e. thelinear range) for a given oscillating inductor as well as all the otherrelated factors or parts' attributes involved in a Boost CCPC PFCSystem, can be establish in less than 30 minutes.

A similarly design for a Closed Loop—Multiplier Controller Circuit(including a P-Spice model for the controller circuit) needs typically5-10 hours of Computer Simulation process, repeated several timeseventually, for optimizing the circuit's parts attributes.

The following Computer Simulation requested about 15 minutes (computertime) and it is by itself an evidence of the CPPC PFC implementation anddesign's simplicity.

FIG. 29A-H illustrates comparatively, a complete Computer Simulationproject, including the schematic diagrams, MOSFET's voltage and currentgraphs, general specs, parts attributes and simulation results of aBoost CPPC PFC AC/DC Converter vs. a classic Bridge Rectifier-BulkCapacitor AC/DC Converter.

The purposes of running this Computer Simulation Project were to reach abrief estimation of the main specs' improvements (i.e. lac (Arms),Apparent Power (VA), PF), a brief image of the MOSFET transistor'stiming diagrams and also a brief estimation of the main partsattributes, including size and cost.

The Simulations' Results presented below are self-explanatory: Iac Pin-RPin-A PF Rload Vo Po Circuit Vac (Vrms) (Arms) (W) (VA) (—) (ohms) (V)(W) Classic (No 120 2.65 165.80 320.00 0.518 160.0 160.6 161.3 PFC) CPPCBoost 120 1.47 176.50 177.50 0.994 900.0 390.2 169.2 PFC Eff. Pulse QpdMOSFET Coil Circuit (%) (uS) (W) (IRF) (uH) Classic (No 97.3 N/A N/A N/AN/A PFC) CPPC Boost 95.9 3.3/10 uS 2.9 740 80 PFC

As the above data show, the CPPC method can be easily implemented inhigh performances (PF=0.994, Eff. >95%) boost system, by using aparticularly low inductance (also low cost) oscillating coil (80 uH) atan easy to reach operating frequency (F=100 KHz, T=4.3/10 uS) and a lowcost MOSFET transistor (IRF 740) which dissipates just 2.9w (low sizeand cost heat sink) for delivering 170w output power range.

All the above items are completing the basic design for the Boost CPPCPFC-IC (50) block schematic diagram version, which is an importantsubject of the present invention.

Together with a complete novel Controller Circuit (i.e. NEWCTRL 100),more details about the above circuit will be further described in theApparatus Embodiment section, as a further subject of the presentinvention.

FIG. 36H shows the Bench Data (including the current vs. voltage TimingDiagram) of the present invention's prototype, in its open loopconfiguration (Vac=120Vrms).

The Bench Data fully confirm the performances of the CPPC Method appliedto a Boost CPPC PFC System and its Computer Simulation components'attributes:

-   PF=0.994, Eff. 95%, T=3.7/10 uS, L1=80 uH    10.4 Conclusions

The above embodiment description introduces the boost version of theCPPC PFC-IC (50) block as an important sub-circuit of a Low Cost HighPerformances Power Factor Correction Circuit (1), which is the mainsubject of the present invention and includes, in different structuraldesigns or system's versions, all the embodiments presented in thispatent application.

Despite the fact that the Constant Pulse Proportional Current Methodprovides simple and cost effective solutions (no “Multiplier”sub-circuit included), the Computer Simulations and Bench Prototypes'Test Data show remarkable results, which are equal or even superior tothe one presented in the High Performances PFC Circuit and Test Dataregarding the Related Art PCF controller—MC 33368.

The advantages of using a Boost CPPC PFC-IC (50) are: low cost, highperformances, fast and simply design, better reliability, less partscount, smaller inductor, smaller size and good efficiency of the entireunit.

The only inconvenient of using a Boost CPPC PFC-IC (50) block in thefact that for a PF>0.99 its output voltage must be much higher(preferable 1.5-2 times) than the maximum (peak) input voltage. FurtherCPPC embodiments will shows different ways of resolving this issue, insituations when a lower output voltage is an imperative.

More details regarding the applications of the CPPC Method implementedin a PFC System will be exposed during the presentation of the furtherembodiments, Computer Simulations and the bench prototype's data sheets.

Other boost versions of CPPC PFC-IC (50) block are used as highperformances references for the next three versions (i.e. Buck, HES andVD-Boost) of the CPPC PFC-LSC (50) System's computer simulations, andalso for the apparatus bench data sheets.

The Buck-Boost CPPC PFC—Inverter Circuit Embodiment

11.1 General Description

FIG. 11 illustrates, in accordance with the present invention, a LowCost High Performances Power Factor Correction System LCHPPFCS (1),comprising a Power Factor Correction Large Signal Circuit PFC-LSC (2)and a Power Factor Correction Small Signal Circuit PFC-SSC (3). ThePFC-LSC (2) comprises, typically an alternative current Voltagegenerator Vac (10), a Low (frequency) Pass Filter block LPF (20), aBridge Rectifier block BR, (30) a Complex Load block CL (40), and abuck-boost Constant Pulse Proportional Current Power Factor CorrectionInverter Circuit block CPPC PFC-IC (50).

The PFC-SSC (3) comprises, typically a Constant Pulse ProportionalCurrent Controller Circuit CPPC CC (100) and a Controller RelatedCircuit (110), however in this specific embodiment; it consists in justa “Constant (frequency, duty/cycle and amplitude) Pulse” square wavegenerator. For the reminder of this description the particularly subcircuit presented as CPPC PFC-CC (100) may be referred to as NEWCTRL(100) as a further subject of the present invention and importantsub-circuit of the LCHPPFCS (1).

The following description refers mainly to the implementation of a CPPCPFC Method into a LCHPPFCS (1) which requests in the LSC section, abuck-boost CPPC PFC-IC (50) block and in the SSC section, a Constant(frequency, duty/cycle and amplitude) Pulse square wave generatorNEWCTRL (100).

For the remainder of this description, the particular sub-circuitpresented as CPPC PFC-IC (50) block, may be referred to as a Buck-BoostCPPC PFC-IC (50), as a subject of the present invention and importantsub-circuit of this LCHPPFCS (1) embodiment version. Other embodimentversions for the LSC section as well as for the SSC section will befurther described.

11.2 The Buck—Boost CPPC PFC LSC Embodiment

Reference will now be made in detail to an embodiment of the invention,illustrated in the accompanying drawing. In accordance with the presentinvention, in FIG. 10 a LCHPPFCS (1) Embodiment is provided, comprisinga PFC-LSC (2) and a PFC-SSC (3). The PFC-LSC (2) includes, in thisembodiment's version, an alternative current Voltage generator Vac (10),a Low (frequency) Pass Filter block LPF (20), a Bridge Rectifier blockBR (30), a Complex Load block CL (40) and a Boost CPPC PFC-IC (50).

The PFC-SSC (3) includes, in this embodiment's version, just a constantfrequency-constant duty/cycle square wave's generator, as arepresentation of a new CPPC PCF Controller Circuit—NEWCTRL (100).

The Vac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms)sine wave voltage generators which provides a full rectified AC voltageto CPPC PFC-LSC (50), trough the LPF (20), comprising two filtratingcapacitor Cf1 (21) and Cf2 (23) flanking a symmetrical double coil Lf1(22) and also through the BR (30), comprising four rectifier diodes DR1(31), DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to a bulk(100-470 uF) capacitor Cb (42), is supplied by (and/or trough) the BoostCPPC PFC-IC (50) block.

The NEWCTRL (100) is (in this embodiment) just a simple high frequency(30-500 KHz) low voltage (12-20V) square wave generator, providing a“Constant Pulse” in amplitude, frequency and duty cycle.

The Boost CPPC PFC-IC (50), as embodied herein, is a complex functionalblock having two input power electrodes Vin+ (51), Vin− (52), two outputpower electrodes Vo− (53), Vo+ (54) and a control electrode DRVin (58).

The figures suggest that the Boost CPPC PFC-IC (50) improves the powerfactor in this circuit and the positions of the various terminals denotethe function of each of them. In other words, in a CPPC PFC-IC (50)schematic diagram, the internal architecture and the positions of theterminals will illustrate, alone, the particular function of eachterminal. Internally, the Boost CPPC PFC-IC (50) block, as embodiedherein, contains a two terminals oscillating coil L1 (61), a highfrequency (30-500 kHz) fast rectifier diode D1 (62), a high power highfrequency (30-500 kHz) MOSFET transistor M1 (63) and a capacitor CVin(64).

The coil L1 (61) has one terminal coupled to Vin+ (51) and the other onecoupled to the anode of D1 (62). The cathode of D1 (62) is coupled toVo+ (54). M1 (63) has its drain electrode coupled to the anode of D1(62), its source electrode to Vin− (52) and its gate electrode coupledto DRVin (58). CVin (64) is coupled across Vin+ (51) and Vin− (52). Vin−(52) is coupled to the system's ground GND (60). Vin+ (51) is coupled toVo− (53).

The BR (30) has its AC input coupled to the LPF (20) output, itspositive output coupled to Vin+ (51) and its negative output to Vin−(52). The CL (40) is coupled across the two output electrodes, Vo+ (54)and Vo− (53). The NEWCTRL(100) is coupled to DRVin (58) in respect toGND (60) via two PFC SSC (3) electrodes, respectively DRV (107) and GND(105).

The Buck-Boost CPPC PFC-IC (50) block and the NEWCTRL (100), as embodiedherein, act together as the LCHPPFCS (1) specific sub-circuits, able toimprove near unity (PF>0.99) the power factor in a circuit, by the meansof an internal Constant Pulse Proportional Current Control Method, whichforces the current waveform shape to follow the voltage waveform shape,in an electrical AC Generator—Complex Load Circuit.

As further embodied herein, when a voltage is applied to the CPPCBuck-Boost PFC-LSC (3) having the positive polarity at Vin+ (51) and thenegative polarity at Vin− (52) and M1 (63) is OFF, no voltage is createdacross the complex load CL (40), respectively across Vo+ (54) and Vo−(53), because there is no current in the Vin+ (51), L1 (61), M1 (63),Vin− (52) circuit (except a very small current in CVin and probably somevery small residual current thru M1 circuit).

When NEWCTRL (100) starts commuting M1 (63) ON/OFF with a high frequency(30-200 kHZ), the DC voltage level across CL (40) will reach a DCvoltage in an amount higher or lower than the input peak voltage,because of the electrical energy stored periodically by L1 (61) duringthe ON time of M1 (63) and delivered periodically, via D1 (62) to CL(40), during the OFF time of M1 (63).

If the charging/discharging time is constant in frequency and duty/cycleand the ON time is short (end/or the OFF time is long) enough forkeeping the coil L1 (61) within its linear range (in other words toprevent the coil's core saturation), then the L1 (61) circuit's currentis direct proportional to the amount of its supply voltage. The value ofCVin (64) is too small to alter significantly the system's power factor,but large enough (100-220 nF) for protecting BR (30) for reverse highfrequency oscillations.

Since the voltage inputted at Vin+ (51) is a full rectified sine waveand there is no bulk capacitor included in the BR (30) output circuit,the L1 (61) circuit's momentary current's value must follow a rectifiedsine wave's shape.

Therefore, in a Buck-Boost version of the CPPC PFC-LSC (2), the Vac (10)current shape is similarly to the one illustrated in FIG. 26, E (almosta sine wave) for any Vout/Vin ratio and without a need for a classic“Multiplier” to be involved in the controller circuit.

If the NEWCTRL (100) frequency and duty/cycle are properly set (see FIG.27A 1-4), in respect to the L1 (61) inductance, max Vin and the max loadcurrent, then the M1 drain voltage shape could be any of the onesillustrated in FIG. 27B 1-4 and the M1 drain current shape could be anyof the ones illustrated in FIG. 27C 1-4 (discontinuous mode ofoperation).

However, if the NEWCTRL (100) frequency and duty/cycle are not properlyset (i.e. OFF time to short and/or ON time too long—see FIG. 27A 5), inrespect to the L1 (61) inductance, max Vin and the max load current,then the M1 drain voltage shape could be the one illustrated in FIG. 27B5 and the M1 drain current shape could be the one illustrated in FIG.27C 5 (continuous mode of operation).

For a high Power Factor parameter (i.e. 0.999) the mode of operationsmust remain unchanged during, at least one Vac (10) semi cycle.

11.3 Design and Implementation

The implementation of the Constant Pulse Proportional Current PowerFactor Correction method in an AC/DC converter is much simple than anyother related art methods (especially the ones involving a Multiplier),providing considerable flexibility in design and parts selection.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, working temperature and even cost price, before the decision ofbuilding a bench prototype is taken.

By having the opportunity to simulate an Open Loop circuit (no P-Spicecontroller model, but just a simple generator providing to the MOSFET a“Constant Pulse”), the proper frequency, the max duty/cycle (i.e. thelinear range) for a given oscillating inductor as well as all the otherrelated factors or parts' attributes involved in a CCPC Buck Boost PFCSystem, can be establish in less than 30 minutes.

A similarly design for a Closed Loop—Multiplier Controller Circuit(including a P-Spice model for the controller circuit) needs typically5-10 hours of Computer Simulation process, repeated several timeseventually, for optimizing the circuit's parts attributes.

The following Computer Simulation requested about 15 minutes computertime and it is by itself an evidence of the CPPC PFC implementation anddesign's simplicity.

FIGS. 30A-H presents comparatively, a complete Computer Simulationproject, including the schematic diagrams, MOSFET's voltage and currentgraphs, general specs, parts attributes and simulation results of a CPPCPFC Boost AC/DC Converter vs. a CPPC PFC Buck-Boost AC/DC Converter.

The main purposes of running this Computer Simulation Project were toreach a brief estimation of the Power Factor parameter amount at a lowVout/Vin(max) ratio (215V/170V=1.25) for a Buck Bust vs. Boost circuit.A brief image of the MOSFET transistor's timing diagrams and the mainparts attributes, (including size and cost) were also important designtargets of this simulation.

The Simulations' Results presented below are self-explanatory: Iac Pin-RPin-A PF Rload Vo Po Circuit Vac (Vrms) (Arms) (W) (VA) (—) (ohms) (V)(W) CPPC 120 1.56 177.90 188.00 0.946 270.0 215.4 171.9 Boost PFC CPPCBuck- 120 1.53 183.10 183.50 0.998 270.0 215.3 171.6 Boost PFC Eff.Pulse Qpd MOSFET Coil Circuit (%) (uS) (W) (IRF) (uH) CPPC 96.6 2.2/10uS 1.15 740 80 Boost PFC CPPC Buck- 93.7 4.3/10 uS 4.15 740 80 Boost PFC

As the above data show, the CPPC method can be easily implemented in ahigh performances Buck-Boost PFC circuit providing a high Power Factor(0.998 vs. just 0.946 for Boost), by using a particularly low inductance(low size and cost) oscillating coil (80 uH) at an easy to reachoperating frequency (F=100 KHz, T=4.3/10 uS), reasonable Efficiency(93.7%) and a low cost MOSFET transistor (IRF 740). However the MOSFETdissipation in Buck-Boost configuration (4.15w) is over three timeshigher than in Boost case (1.15w). The size and cost of the MOSFET'sheat sink must increase accordingly.

All the above items are completing the basic design for the buck-boostversion of the CPPC PFC-LSC (50) schematic diagram, which is anotherimportant subject of the present invention.

11.4 Conclusions

Despite the fact that the Constant Pulse Proportional Current methodprovides simple and cost effective solutions, the Computer Simulationsand Bench Prototypes' Test Data show remarkable results, which are equalor even superior to the one presented in the High Performances PFCCircuit and Test Data (Related Art—MC 33368).

The above embodiment description introduces the buck-boost version ofthe PFC-LSC (50) as an important sub-circuit of a Low Cost HighPerformances Power Factor Correction Circuit (1), which is actually themain subject of the present invention and includes, in differentstructural designs or system versions, all the embodiments presented inthis patent application.

The advantages of using a buck-boost version of the CPPC PFC-LSC (3)are: no restrictions for the output voltage level, low cost, highperformances (PF, THD), fast and simply design, better reliability, lessparts count, smaller inductor and reasonable efficiency of the entireunit.

The only inconvenient of using a-boost version of the CPPC PFC-LSC (3)consists in the fact that the MOSFET dissipation is 2-3 times higher inrespect to a CPPC Boost configuration, fact which decreases (1-3%) theefficiency of the entire circuit.

However, in situations when a low output voltage is an imperative, theBuck-Boost configuration remains the optimal solution.

More details regarding the applications of the CPPC method implementedin a PFC System will be exposed during the presentation of the furtherembodiments, Computer Simulations and the Apparatus prototype's BenchData Sheets.

The HES—Boost CPPC PFC—Inverter Circuit Embodiment

12.1 General Description

FIG. 12 illustrates, in accordance with the present invention, a LowCost High Performances Power Factor Correction System—LCHPPFCS (1),comprising a Power Factor Correction Large Signal Circuit PFC-LSC (2)and a Power Factor Correction Small Signal Circuit PFC-SSC (3).

The PFC-LSC (2) comprises, typically an alternative current Voltagegenerator Vac (10), a Low (frequency) Pass Filter block LPF (20), aBridge Rectifier block BR, (30) a Complex Load block CL (40), and a highefficiency snubber-boost Constant Pulse Proportional Current PowerFactor Correction Inverter Circuit block CPPC PFC-IC (50).

The PFC-SSC (3) comprises, typically a Constant Pulse ProportionalCurrent Controller Circuit CPPC CC (100) and a Controller RelatedCircuit (110), however in this specific embodiment, it consists in justa “Constant (frequency, duty/cycle and amplitude) Pulse” square wavegenerator. For the reminder of this description the particularly subcircuit presented as CPPC PFC-CC (100) may be referred to as NEWCTRL(100) as a further subject of the present invention and importantsub-circuit of the LCHPPFCS (1).

The following description refers mainly to the implementation of a CPPCPFC Method into a LCHPPFCS (1) which requests in the LSC section, a highefficiency snubber-boost CPPC PFC-IC (50) block and in the SSC section,a Constant (frequency, duty/cycle and amplitude) Pulse square wavegenerator NEWCTRL (100).

For the remainder of this description, the particularly sub-circuitpresented as CPPC PFC-IC (50) block, may be referred to as a HES-BoostCPPC PFC-IC (50), as a subject of the present invention and importantsub-circuit of this LCHPPFCS (1) embodiment version.

Other embodiment versions for the LSC section as well as for the SSCsection will be further described, in the next chapters of the presentinvention.

12.2 The HES—Boost CPPC PFC LSC Embodiment

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 11 a Low Cost HighPerformances Power Factor Correction Circuit—LCHPPFCC (1) Embodiment isprovided, comprising a PFC-LSC (2) and a PFC-SSC (3).

The PFC-LSC (2) includes, in this embodiment version, an alternativecurrent Voltage generator Vac (10), a Low (frequency) Pass Filter blockLPF (20), a Bridge Rectifier block BR (30), a Complex Load block CL(40), a High Efficiency Snubber-Boost Constant Pulse ProportionalCurrent Power Factor Correction Inverter Circuit block HES-Boost CPPCPFC-IC (50).

The PFC-SSC (3) includes, in this embodiment version, just aconstant-constant duty/cycle square wave generator, as a symbol of anovel CPPC PFC Controller Circuit—NEWCTRL (100).

The Vac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms)sine wave voltage generators which provides a full rectified AC voltageto CPPC PFC-LSC (50), trough the LPF (20), comprising two filtratingcapacitor Cf1 (21), Cf2 (23) flanking a symmetrical double coil Lf1 (22)and also trough the BR (30), comprising four rectifier diodes DR1 (31),DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to a bulk(100-470 uF) capacitor Cb (42), is supplied by (and/or trough) the CPPCPFC-LSC (50) block,

The NEWCTRL (100) is, in this embodiment, just a simple high frequency(30-500 KHz) low voltage (12-20V) square wave generator, which providesa “Constant Pulse” in amplitude, frequency and duty cycle.

The HES-Boost CPPC PFC-IC (50), as embodied herein, is a complexfunctional block having two input power electrodes Vin+ (51), Vin− (52),two output power electrodes Vo− (53), Vo+ (54) and a control electrodeDRVin (58).

The figures suggest that the HES-Boost CPPC PFC-IC (50) improves thepower factor in this circuit and the positions of the various terminalsdenote the function of each of them. In other words, in a CPPC PFC-IC(50) schematic diagram, the internal architecture and the positions ofthe terminals will illustrate, alone, the particular function of eachterminal.

Internally, the HES-Boost CPPC PFC-IC (50) block, as embodied herein,contains a two terminals oscillating coil L1 (61), a high frequency(30-500 kHz) fast rectifier diode D1 (62), a high power high frequency(30-500 kHz) MOSFET transistor Ms (63) and a capacitor CVin (64). Also aHigh Efficiency Snubber circuit comprising a first snubber diode Ds1(66), a two terminals snubber coil Ls (67), a snubber capacitor Cs (68)and a second snubber diode Ds2 (69), is attached to the above boostconverter.

The coil L1 (61) has one terminal coupled to Vin+ (51) and the other onecoupled to the anode of D1 (62). The cathode of D1 (62) is coupled toVo+ (54). Ms (63) has its drain electrode coupled to the anode of D1(62), its source electrode to Vin− (52) and its gate electrode coupledto DRVin (58). CVin (64) is coupled between Vin+ (51) and Vin− (52).Vin− (52) is coupled to the system's ground GND (60) and also to Vo−(53).

In addition, Ds1 (66) has its anode coupled to Vin+ (51) and its cathodecoupled to the anode of Ds2 (69) via Ls (67). The cathode of Ds2 (69) iscoupled to Vo+ (54). Cs (68) is coupled between the anode of Ds2 (69)and the anode of D1 (62).

The BR (30) positive output is coupled to Vin+ (51) and its negative oneto Vin− (52).

The CL (40) is coupled across the two output electrodes, Vo+ (54) andVo− (53).

The NEWCTRL (100) is coupled to DRVin (58) in respect to GND (60).

The HES-Boost CPPC PFC-IC (50) block and the CPPC PFC-CC (100), asembodied herein, act together as a LCHPPFCS (1) able to improve nearunity (PF>0.99) the power factor in a circuit, by the means of aninternal Constant Pulse Proportional Current Control Method, whichforces the current waveform shape to follow the voltage waveform shape,in an electrical AC Generator—Complex Load Circuit.

As further embodied herein, when a voltage is applied to the CPPCHES—Boost PFC-LSC (4) having the positive polarity at Vin+ (51) and thenegative polarity at Vin− (52) and Ms (63) is OFF, a DC voltage iscreated across the complex load CL (40), respectively across Vo+ (54)and Vo− (53), in an amount slightly lower than the peak input voltage(classic Bridge Rectifier-Bulk Capacitor AC/DC Converter). As has beenexplained in the Related Art section, the Vac (10) current shape in thiscircuit is similarly to the one shown in FIG. 26, B and the PF is about0.65 or less.

When the NEWCTRL (100) starts commuting Ms (63) ON/OFF with a highfrequency (30-200 kHZ), the DC voltage level at Vo (54) will increase toa higher amount than the input peak voltage, because of the electricalenergy stored periodically by L1 (61), Ls (67) and Cs (68) during the ONtime of Ms (63) and delivered periodically via D1 (62), Ds2 (69) to CL(40), during the OFF time of Ms (63). The value of CVin (64) is toosmall to alter the system's power factor, but large enough (100-220 nF)for protecting BR (30) for reverse high frequency oscillations.

As soon Cb (42) is charged up to a higher value than the input peakvoltage, there is no more direct current between Vac (10) and CL (40),because BR (30), Ds1 (66), Ds2 (69) and D1 (62) are reverse polarized.Starting from this moment, the circuit's input current shape depends ofthe L1 (61) parallel with Ls (67)-Cs (68) circuit's current only.

In other words, the Vac (10) does not “feel” anymore in its circuit thebulk capacitor Cb (42), which is the only one device able to reducesubstantially the entire circuit's power factor.

If the charging/discharging time is constant in frequency and duty/cycleand the ON time is short enough for keeping the coils L1 (61) and Ls(67) within the linear range (in other words to prevent the coils' coressaturation), then the L1 (61), L2 (67) circuit's current is directproportional to the amount of its supply voltage.

Since the voltage inputted at Vin+ (51) is a full rectified sine wave,the L1 (61) and Ls (67) circuit's momentary current's value must followa rectified sine wave's shape.

Therefore, as soon the output voltage is higher (preferable 1.5-2 times)than the input peak voltage, the Vac (10) current shape changesimmediately to a form similarly to the one illustrated in FIG. 26, E(almost a sine wave) without a need for a classic “Multiplier” to beinvolved in the controller circuit.

If the NEWCTRL (100) frequency and duty/cycle are properly set (see FIG.27A 1-4), in respect to the L1 (61) and Ls (67) inductance, Cs value,max Vin and the max load current, then the Ms drain voltage shape couldbe any of the ones illustrated in FIG. 27E 1-4 and the Ms drain currentshape could be any of the ones illustrated in FIG. 27F 1-4(discontinuous mode of operation).

However, if the NEWCTRL (100) frequency and duty/cycle are not properlyset (i.e. OFF time too short and/or ON time too long—see FIG. 27A 5), inrespect to the L1 (61) and Ls (67) inductance, Cs value, max Vin and themax load current, then the Ms drain voltage shape may be the oneillustrated in FIG. 27E 5 and the Ms drain current shape may be the oneillustrated in FIG. 27F 5 (continuous mode of operation).

For a high Power Factor parameter (i.e. 0.999) the mode of operationsmust remain unchanged during, at least one Vac (10) semi cycle.

12.3 Design and Implementation

The implementation of the Constant Pulse Proportional Current PowerFactor Correction method in an AC/DC converter is much simple than anyother related art methods (especially the ones involving a Multiplier),providing considerable flexibility in design and parts selection.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, working temperature and even cost price, before the decision ofbuilding a bench prototype is taken.

By having the opportunity to simulate an Open Loop circuit (no P-Spicecontroller model, but just a simple generator providing to the MOSFET a“Constant Pulse”), the proper frequency, the max duty/cycle (i.e. thelinear range) for the given oscillating inductor's as well as all theother related factors or parts' attributes involved in a HES-Boost CCPCPFC System, can be establish in less than 30 minutes.

A similarly design for a Closed Loop—Multiplier Controller Circuit(including a P-Spice model for the controller circuit) needs typically5-10 hours of Computer Simulation process, repeated several timeseventually, for optimizing the circuit's parts attributes.

The following Computer Simulation requested about 20 minutes computertime and it is by itself an evidence of the CPPC PFC implementation anddesign's simplicity.

FIG. 31A-J illustrates comparatively, a complete Computer Simulationproject, including the schematic diagrams, MOSFET's voltage and currentgraphs, general specs, parts attributes and simulation results of aHES-Boost CPPC PFC AC/DC Converter vs. a Boost CPPC PFC AC/DC Converter.

The main purposes of running this Computer Simulation Project were toreach a brief estimation of the MOSFET's dissipation for a HES-Bust vs.Boost circuit. A brief image of the MOSFET transistor's timing diagramsand the main parts attributes, (including size and cost) were alsoimportant design targets of this simulation.

The Simulations' Results presented below are self-explanatory: Iac Pin-RPin-A PF Rload Vo Po Circuit Vac (Vrms) (Arms) (W) (VA) (—) (ohms) (V)(W) CPPC 120 1.79 212.50 214.70 0.990 450.0 300.3 200.4 Boost PFC CPPCHES- 120 1.76 209.40 211.10 0.992 450.0 300.4 200.5 Boost PFC Eff. PulseMpd MOSFET Rds (ON) Coil Circuit (%) (uS) (W) (IRF) ohms (uH) CPPC 94.35.7/14 uS 5.6 840 0.85 172 Boost PFC CPPC HES- 95.7 5.7/14 uS 1.8 8400.85 215 + 125 Boost PFC

As the above data show, the CPPC Method can be easily implemented in ahigh performance HES-Boost PFC System. The circuit provides a lowerMOSFET's heat dissipation (1.8w vs. 5.6w for Boost) and a betterefficiency (95.7% vs. 94.3% for Boost) by the means of a snubber circuitincluding one coil, one capacitor and two diodes. A high Power Factor(0.992), an easy to reach operating frequency (F=70 KHz, T=5.7/14 uS),and a low cost MOSFET transistor (IRF 840) are also important featuresof this circuit.

Observation: IRF840 has higher drain-source ON resistance (0.85 ohms)than IRF740 (0.53 Ohms), so an Eff=95.7% is a very good one for thisparticularly PFC System, which has a loss of over 2% in the Bridgerectifier's and the Low Pass Filter's devices.

All the above items are completing the basic design for the CPPCHES-Boost PFC-LSC (4) schematic diagram, which is another importantsubject of the present invention.

All the above items are completing the basic design for the CPPC BoostPFC-Large Signal Circuit (1) schematic diagram, which is an importantsubject of the present invention.

12.4 Conclusions

Despite the fact that the Constant Pulse Proportional Current methodprovides simple and cost effective solutions, the Computer Simulationsand Bench Prototypes' Test Data show remarkable results, which are equalor even superior to the one presented in the High Performances PFCCircuit and Test Data (Related Art—MC 33368).

The above embodiment description introduces the HES-boost version of theCPPC PFC-LSC (50) as an important sub-circuit of a Low Cost HighPerformances Power Factor Correction System (1), which is actually themain subject of the present invention and includes, in differentstructural designs or system versions, all the embodiments presented inthis patent application.

The advantages of using a HES-Boost version of the CPPC PFC-LSC (50)are: low cost, high performances, fast and simply design, betterreliability, less parts count, smaller heat sink size and very goodefficiency of the entire unit.

In respect to the classic Snubber circuit described at the Related Artsection (FIG. 9), the High Efficiency Snubber circuit provides thefollowing advantages:

-   1. HES is a “Loss Less Snubber” circuit, because does not include    resistors or any other dissipative devices.-   2. HES allows for using much larger value capacitors (10-47 nF in    respect to 0.5-5 nF in classic situation), so the delay of the    MOSFET transistor's drain fast voltage increasing course (described    at the Related Art section) can be much longer (see FIG. 27E vs.    FIG. 27B). As a positive result, the momentary value of the Ms    (HES-Boost) power (FIG. 27G, VMs:d)×I(Ms:d)=20W) for each high    frequency cycle is about 100 times lower than momentary value of the    M1 (Boost) power (FIG. 27D, VM1:d)×I(M1:d)=2 kW), fact which    significantly decrease the MOSFET dissipation.-   3. The snubber capacitor Cs (68) is periodically charged with a high    DC voltage which forces the main coil L1 (61) to discharge a larger    percent (than in classic boost circuit) of its own stored energy,    via Cs (68) and Ds2 (69) into the CL (40) circuit.-   4. The Ms drain current's shape is almost a rectangle (FIG. 27F) in    respect to the M1 drain current's shape which is a triangle (FIG.    27C). The rectangle form allows for lower peak current and is more    efficient (less heat dissipation in the MOSFET) than the triangle    current shape.

The disadvantage of using a HES-Boost version of the CPPC PFC-IC (50)consist in the fact that by attaching four extra parts, the cost and theparts count factor will increase accordingly.

More details regarding the implementation of the CPPC Method in a PFCSystem will be exposed during the presentation of the furtherembodiments, Computer Simulations and the Apparatus prototype's BenchTest Data Sheets.

The VD—Boost CPPC PFC—Inverter Circuit Embodiment

13.1 General Description

FIG. 13 illustrates, in accordance with the present invention, a LowCost High Performances Power Factor Correction System—LCHPPFCS (1),comprising a Power Factor Correction Large Signal Circuit PFC-LSC (2)and a Power Factor Correction Small Signal Circuit PFC-SSC (3).

The PFC-LSC (2) comprises, typically an alternative current Voltagegenerator Vac (10), a Low (frequency) Pass Filter block LPF (20), aBridge Rectifier block BR, (30) a Complex Load block CL (40), and avoltage doubler-boost Constant Pulse Proportional Current Power FactorCorrection Inverter Circuit block CPPC PFC-IC (50).

The PFC-SSC (3) comprises, typically a Constant Pulse ProportionalCurrent Controller Circuit CPPC CC (100) and a Controller RelatedCircuit (110), however in this specific embodiment, it consists in justa “Constant (frequency, duty/cycle and amplitude) Pulse” square wavegenerator. For the reminder of this description the particularly subcircuit presented as CPPC PFC-CC (100) may be referred to as NEWCTRL(100) as a further subject of the present invention and importantsub-circuit of the LCHPPFCS (1).

The following description refers mainly to the implementation of a CPPCPFC Method into a LCHPPFCS (1) which requests in the LSC section, avoltage doubler-boost CPPC PFC-IC (50) block and in the SSC section, a“Constant (frequency, duty/cycle and amplitude) Pulse” square wavegenerator NEWCTRL (100).

For the remainder of this description, the particularly sub-circuitpresented as CPPC PFC-IC (50) block, may be referred to as a VD-BoostCPPC PFC-IC (50), as a subject of the present invention and importantsub-circuit of this LCHPPFCS (1) embodiment version.

Other embodiment versions for the LSC section as well as for the SSCsection will be further described, in the next chapters of the presentinvention.

13.2 The VD—Boost CPPC PFC LSC System Embodiment

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 13 a Low Cost HighPerformances Power Factor Correction Circuit—LCHPPFCC (1) Embodiment isprovided, comprising a PFC-LSC (2) and a PFC-SSC (3).

PFC-LSC (2) includes, in this embodiment version, an alternative currentVoltage generator Vac (10), a Low (frequency) Pass Filter block LPF(20), a Bridge Rectifier block BR (30), a Complex Load block CL (40), aVoltage Doubler—Boost Constant Pulse Proportional Current Power FactorCorrection Large Signal Circuit block CPPC PFC-LSC (50).

The PFC-SSC (3) includes, in this embodiment version, just a constantfrequency-constant duty-cycle square wave generator, as a symbol of anovel CPPC PCF Controller Circuit—NEWCTRL (100).

The Vac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms)sine wave voltage generators which provides a full rectified AC voltageto VD-Boost CPPC PFC-IC (50), trough the LPF (20), comprising twofiltrating capacitor Cf1 (21), Cf2 (23) flanking a symmetrical doublecoil Lf1 (22) and also trough the BR (30), comprising four rectifierdiodes DR1 (31), DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to two bulk(100-470 uF each) capacitors Cb1 (43), Cb2 (44) is supplied by (and/ortrough) the VD-Boost CPPC PFC-IC (50) block.

NEWCTRL (100) is, in this embodiment, just a simple high frequency(30-500 KHz) low voltage (12-20V) square wave generator, which providesa “Constant Pulse” in amplitude, frequency and duty cycle.

The VD-Boost CPPC PFC-IC (50), as embodied herein, is a complexfunctional block having three input power electrodes Vin+ (51), Vin0(55), Vin− (52), three output power electrodes Vo− (53), Vo0 (56), (Vo+(54) and a control electrode DRVin (58).

The figures suggest that the VD-Boost CPPC PFC-IC (50) improves thepower factor in this circuit and the positions of the various terminalsdenote the function of each of them. In other words, in a CPPC PFC-IC(50) schematic diagram, the internal architecture and the positions ofthe terminals will illustrate, alone, the particular function of eachterminal.

Internally, the VD-Boost version of the CPPC PFC-IC (50) has a symmetricarchitecture containing a first two terminals oscillating coil L1 (71),a second two terminals oscillating coil L2 (81), a first high frequencyrectifier diode Do1 (72), a second high frequency rectifier diode Do2(82), a first MOSFET transistor M1 (73), a second MOSFET transistor M2(83), a first input capacitor CVin+ (74), a second input capacitor CVin−(84) and a one input (Lf1)—two output (Lf2, Lf3) coils high frequencytransformer TR1 (75).

The coil Lo1 (71) has one terminal coupled to Vin+ (51) and the otherone coupled to the anode of Do1 (72). The cathode of Do1 (72) is coupledto Vo+ (54). M1 (73) drain electrode is coupled to the anode of Do1 (72)and M1 source electrode is coupled to Vin0 (55). CVin+ (74) is coupledbetween Vin+ (51) and Vin0 (55).

The coil Lo2 (81) has one terminal coupled to Vin− (52) and the otherone coupled to the cathode of Do2 (82). The anode of Do2 (82) is coupledto Vo− (53). M2 (83) drain electrode is coupled Vin0 (55) and M2 sourceelectrode is coupled to the cathode of Do2 (82). CVin− (84) is coupledbetween Vin− (52) and Vin0 (55). Vin0 (55) is coupled to GND (60) andalso to Vo0 (56).

The TR1 (75) has its primary coil (L1) coupled between Vin0 (55) andDRVin (58), one of its secondary coil (Lf2) coupled across M1 (73)drain-source electrodes and the last coil (Lf3) coupled across M2 (83)drain-source electrodes.

The BR (30) positive output is coupled to Vin+ (51) and its negative oneto Vin− (52) and one of its AC inputs coupled to Vin0 (55) and also toGND (60) similarly to the classic voltage doubler circuit (Related artFIG. 3).

The CL (40) is coupled across the two output electrodes, Vo+ (54) andVo− (53) and the middle connections of the two capacitors Cb1 (43), Cb2(44) is connected to Vo0 (56), also similarly to the classic voltagedoubler circuit (Related art FIG. 3).

The CPPC PFC SSC (3) represented by NEWCTRL (100) is coupled to DRVin(58) in respect to GND (60) via two electrodes DRV (107) and GND (105).

The VD-Boost CPPC PFC-IC (50) block and the CPPC PFC-CC (100), asembodied herein, act together as a CPPC PFC System able to improve nearunity (PF>0.99) the power factor in a circuit, by the means of aninternal Constant Pulse Proportional Current Control Method, whichforces the current waveform shape to follow the voltage waveform shape,in an electrical AC Generator—Complex Load Circuit such as LCHPPFCC (1).

As further embodied herein, when a voltage is applied to the boostconfiguration of the VD-Boost CPPC PFC-IC (50) having the positivepolarity at Vin+ (51), zero voltage (no polarity) at Vin0 (55) and thenegative polarity at Vin− (52) and M1 (63) is OFF, a DC voltage iscreated across the complex load CL (40), respectively across Vo+ (54)and Vo− (53), in an amount slightly lower than the double rms inputvoltage (classic Bridge Rectifier—Bulk Capacitor Voltage Doubler AC/DCconverter). As has been explained in the Related Art section, the Vac(10) current shape in this circuit is similarly to the one shown in FIG.26, B and the PF is about 0.65 or less.

When NEWCTRL (100) starts commuting M1 (63) ON/OFF with a high frequency(30-200 kHZ), the DC voltage level across Vo+ (54)-Vo− (53) willincrease to a higher amount than twice peak input voltage, because ofthe electrical energy stored periodically by L1 (71) and L2 (81) duringthe ON time of M1 (73), M2 (83) and delivered periodically, via D1 (72)and Do2 (82) to CL (40), during the OFF time of M1 (73), M2 (83). CVin+(74) and CVin− (84) have too small to alter significantly the system'spower factor, but large enough (100-220 nF each) for protecting BR (30)for reverse high frequency oscillations.

As soon the voltage across Vo+ (54) and Vo− (53) reaches a higher valuethan twice input peak voltage, there is no more direct current betweenVac (10) and CL (40), because BR (30), Do1 (72) and Do2 (82) are reversepolarized. Starting from this moment, the circuit's input current shapedepends of the L1 (71) and L2 (72) circuit's current only.

In other words, the Vac (10) does not “feel” anymore the two bulkcapacitors Cb1 (43) and Cb2 (44), which are the only two device able toreduce substantially the entire circuit's power factor.

If the charging/discharging time is constant in frequency and duty/cycleand the ON time is short (and/or OFF time is long) enough for keepingthe coils L1 (71) L2 (81), within the linear range (in other words toprevent the coils' cores saturation), then the L1 (71) and Lo2 (81)circuit's current momentary amount for each semi-cycle, is directproportional to the amount of its momentary supply voltage amount.

Since the voltage inputted at Vin+ (51) is a full rectified sine wave,the L1 (61) circuit's current time graph must follow a rectified sinewave's shape.

Therefore, as soon the output voltage is higher (preferable 2.5-3 times)than the input peak voltage, the Vac (10) current shape changesimmediately to a form similarly to the one illustrated in FIG. 26E(almost a sine wave) without a need for a classic “Multiplier” to beinvolved in the controller circuit.

If the NEWCTRL (100) frequency and duty/cycle are properly set—i.e. OFFtime not too short and/or ON time not too long—(see FIG. 27A 1-4), inrespect to the Lo1 (71)=Lo2 (81) inductance, max Vin+ and the max loadcurrent, then the M1 (73) and/or M2 (83) drain voltage shape could beany of the ones illustrated in FIG. 27B 1-4 and the M1 (73), M2 (83)drain current shape could be any of the ones illustrated in FIG. 27C1-4, for each of the Vac (10) semi-cycle (discontinuous mode ofoperation).

However, if the NEWCTRL (100) frequency and duty/cycle are not properlyset—i.e. OFF time too short and/or ON time too long—see FIG. 27A 5), inrespect to the Lo1 (71)=Lo2 (81) inductance, max Vin+ and/or Vin− andthe max load current, then the M1 (73) and/or M2 (83) drain voltageshape could be any of the ones illustrated in FIG. 27B 5 and the M1 (73)and/or M2 (83) drain current shape could be the one illustrated in FIG.27C 5 (continuous mode of operation).

For a high Power Factor parameter (i.e. 0.999) the mode of operationsmust remain unchanged during, at least one Vac (10) semi-cycle.

13.3 Design and Implementation

The implementation of the Constant Pulse Proportional Current PowerFactor Correction method in an AC/DC converter is much simple than anyother related art methods (especially the ones involving a Multiplier),providing considerable flexibility in design and parts selection.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, working temperature and even cost price, before the decision ofbuilding a bench prototype is taken.

By having the opportunity to simulate an Open Loop circuit (no P-Spicecontroller model, but just a simple generator providing to the MOSFET'sa “Constant Pulse”), the proper frequency and the max duty/cycle (i.e.the linear range) for a given oscillating inductor as well as all theother related factors or parts' attributes involved in a Boost CCPC PFCSystem, can be establish in less than 30 minutes.

A similarly design for a Closed Loop—Multiplier Controller Circuit(including a P-Spice model for the controller circuit) needs typically5-10 hours of Computer Simulation process, repeated several timeseventually, for optimizing the circuit's parts attributes.

The following Computer Simulation requested about 25 minutes (computertime) and it is by itself an evidence of the CPPC PFC implementation anddesign's simplicity.

FIG. 29A-H illustrates comparatively, a complete Computer Simulationproject, including the schematic diagrams, MOSFET's voltage and currentgraphs, general specs, parts attributes and simulation results of aVD-Boost CPPC PFC circuit vs. a Boost CPPC PFC circuit.

The main purposes of running this Computer Simulation Project were toreach a brief estimation of the Efficiency parameter of a VD-Bust vs.Boost system's configuration and the cost saving, out coming from a muchbetter efficiency. A brief image of the MOSFET transistors' timingdiagrams and the main parts attributes, (including size and cost) werealso important design targets of this simulation.

The Simulations' Results presented below are self-explanatory: lac Pin-RPin-A PF Rload Vo Po Circuit Vac (Vrms) (Arms) (W) (VA) (—) (ohms) (V)(W) Boost CPPC 90 3.52 315.00 316.20 0.996 675.0 449.7 299.6 PFCVD-Boost 90 3.51 312.20 315.80 0.989 675.0 449.8 299.7 CPPC PFC Eff.Pulse Qpd MOSFET MOSFET Coil Circuit (%) (uS) (W) (IRF) $/unit (uH)Boost CPPC 95.1 9.97/16 uS 2.8 2 × 460 5.90 120 PFC VD-Boost 96.07.08/16 uS 2.5 2 × 740 0.88 2 × 86 CPPC PFC

As the above data show, the CPPC method can be easily implemented inhigh performances (PF=0.99, Eff. >96%) VD-Boost CPPC PFC System, byusing a particularly low inductance (also low cost) oscillating coil(2×86uH) at an easy to reach operating frequency (F=62 KHz, T= 7/16 uS)and low cost MOSFET transistors (2×IRF 740=$0.88/unit vs. 2×IRF460=5.90/unit) which dissipate just 2.5w each (low size and cost heatsink) for delivering 300w output power range.

An significant cost saving of about $10/Circuit has been achieve becauseonly the VD-Boost CPPC PFC System can use low drain-source voltageMOSFET's (Vds=400Vmax) such as IRF740. (because Vo=450V/2=225V/MOSFET).

For the same Vo=450V, the Boost CPPC PFC configuration requests aminimum 500Vds MOSFET.

All the above items complete the basic design for the VD-Boost Systemversion of the CPPC PFC-IC (50), which is an important subject of thepresent invention.

13.4 Conclusions

The above embodiment description introduces the VD-Boost version of theCPPC PFC-IC (50) as an important sub-circuit of the LCHPPFCS (1), whichis actually the main subject of the present invention and includes, indifferent structural designs or system's versions, all the embodimentspresented in this patent application.

Despite the fact that the Constant Pulse Proportional Current Methodprovides simple and cost effective solutions (no “Multiplier”sub-circuit included), the Computer Simulations and Bench Prototypes'Test Data show remarkable results, which are equal or even superior tothe one presented in the High Performances PFC Circuit and Test Data(Related Art—MC 33368).

The advantages of using a VD-Boost CPPC PFC-LSC are: very goodefficiency, lower MOSFET's Vds (drain—source voltage), smaller heat sinksize, lower working temperature, low cost at high power, highperformances, fast and simply design, better reliability, smallerinductor.

In order to reach about the same efficiency, in the Boost version wereused much stronger and expensive MOSFETs: (2×IRF460, Vds=500V,Rds(on)=0.27, Cost=$5.90/unit).

By taking advantage of the lower MOSFET's Vds feature, which allows theuse of low cost MOSFETs (i.e. 2×IRF 740, Vds=400V, Rds(on)=0.53,Cost=$0.88/unit) in the VD-Boost version, significant cost saving ofabout $10/System can be achieved.

The main inconvenient of using a VD-Boost CPPC PFC-LSC System consistsin the fact that it requests twice parts count. However, in situationswhere the efficiency, the heat sink size and the working temperature arethe main imperatives for as high power (300-1000w) AC/DC converter, theVD-Boost CPPC PFC system remains the best solution.

More details regarding the applications of the CPPC Method implementedin a PFC System will be exposed during the presentation of the furtherembodiments, Computer Simulations and the bench prototype's data sheets.

The Generic CPPC PFC LSC Embodiment

14.1 General Description

FIG. 14 illustrates, in accordance with the present invention, a LowCost High Performances Power Factor Correction System—LCHPPFCS (1),comprising, typically, a Power Factor Correction Large Signal CircuitPFC-LSC (2) and a Power Factor Correction Small Signal Circuit PFC-SSC(3).

The PFC-LSC (2) comprises, in this embodiment version, an alternativecurrent Voltage generator Vac (10), a Low (frequency) Pass Filter blockLPF (20), a Bridge Rectifier block BR, (30) a Complex Load block CL(40), and a generic boost Constant Pulse Proportional Current PowerFactor Correction Inverter Circuit block CPPC PFC-IC (50) which, in thisembodiment represent the generic complementary sub-circuit for thePFC-SSC (3), in respect to the entire LCHPPFCS (1).

The PFC-SSC (3) comprises, typically a Constant Pulse ProportionalCurrent Controller Circuit CPPC-CC—NEWCTRL (100) and a ControllerRelated Circuit (110), however in this specific embodiment is presentedonly the Controller Self-Supply Circuit CSSC (90) as a sub-circuit ofthe CRC (110), for applications where no other 16-20v DC supply voltageis available. It is worth noting that in most of cases, the LCHPPFCS (1)acts as a PFC voltage pre-regulator for a classic power supply, whichusually provides itself a regulate DC voltage supply, back to theLCHPPFCS (1) controller circuit.

A complete presentation of the CPPC PFC-CC (100) and CRC (110) startsfrom the next chapter (15) of the present patent application, as afurther subject of the present invention and important sub-circuits ofthe LCHPPFCS (1).

The following description refers to a implementation of a CPPC PFCMethod into a LCHPPFCS (1) comprising a complex CPPC PCF SSC (3)sub-circuit (which includes not just a square wave generator, but acomplex multi-block controller and a voltage/current feedback controllerrelated circuit) and therefore a generic CPPC PFC-IC (50) block isprovided, as a representative versions for all the other above describedCPPC PFC-IC sub-circuits, (such as Boost, Buck-Boost, HES-Boost orVD-Boost PFC inverter circuit).

In other words, the same technique of implemented the CPPC PFC ControlMethod in this generic inverter circuit can be used for all the otherinverter versions.

For the remainder of this description, the particularly sub-circuitpresented as a generic CPPC PFC-IC (50) block, may be referred to as aGeneric-Boost CPPC PFC-IC (50), circuit, to be used as a complementarysub circuit for the NEWCTRL (100) and its related circuit.

14.2 The Generic CPPC PFC—LSC Embodiment

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 14 a LCHPPFCS (1)Embodiment is provided, comprising a generic PFC-LSC (2) and aController Self Supply Circuit CSSC (90) block, as an optionalsub-circuit of the PFC-SSC (3).

The other sub-circuits of the PFC-SSC (3), such as the CPPC PFC-CC(NEWCTRL) (100) and the CRC (110), will be in detail presented in thenext chapters, as complementary circuits of the PFC-LSC (2), in respectto the entire LCHPPFCS (1).

The PFC-LSC (2) includes, in this embodiment's version, an alternativecurrent Voltage generator Vac (10), a Low (frequency) Pass Filter blockLPF (20), a Bridge Rectifier block BR (30), a Complex Load block CL (40)and a generic Boost CPPC PFC-IC (50).

The Vac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms)sine wave voltage generators which provides a full rectified AC voltageto CPPC PFC-LSC (50), trough the LPF (20), comprising two filtratingcapacitor Cf1 (21) and Cf2 (23) flanking a symmetrical double coil Lf1(22) and also trough the BR (30), comprising four rectifier diodes DR1(31), DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to a bulk(100-470 uF) capacitor Cb (42), is supplied by (and/or trough) the BoostCPPC PFC-IC (50) block.

The Boost CPPC PFC-IC (50), as embodied herein, is a complex functionalblock having seven I/O electrodes, respectively two large signal inputelectrodes Vin+ (51), Vin− (52), two large signal output powerelectrodes Vo− (53), Vo+ (54) and three small signal electrodes such asVps (57), DRVin (58) and VRs (59).

The figures suggest that the Boost CPPC PFC-IC (50) improves the powerfactor in this circuit and the positions of the various terminals denotethe function of each of them. In other words, in a CPPC PFC-IC (50)schematic diagram, the internal architecture and the positions of theterminals will illustrate, alone, the particular function of eachterminal.

Internally, the Generic Boost CPPC PFC-IC (50) block, as embodiedherein, contains a two terminals oscillating coil L1 (61) mutual coupledto the controller's supply coil Lsc (99), a high power fast (30-500 kHz)rectifier diode D1 (62), a high power high frequency (30-500 kHz) MOSFETtransistor M1 (63), a sense resistor Rs (65) and a capacitor CVin (64).

The coil L1 (61) has one terminal coupled to Vin+ (51) and the other onecoupled to the anode of D1 (62). The cathode of D1 (62) is coupled toVo+ (54). M1 (63) has its drain electrode coupled to the anode of D1(62), its source electrode to Vin− (52) via Rs (65) and its gateelectrode coupled to DRVin (58). CVin (64) is coupled across Vin+ (51)and Vin− (52). Vin− (52) is coupled to Vo− (53) and is also coupled tothe system's ground GND (60).

The BR (30) has its AC input coupled to the LPF (20) output, itspositive output coupled to Vin+ (51) and its negative output to Vin−(52). The CL (40) is coupled across the two output electrodes, Vo+ (54)and Vo− (53). The controller self supply circuit block CSSC (90) hasfour I/O electrodes such as an alternative current high frequency lowvoltage (16-25V) input electrode CSSCac (91), a DC positive voltagesupply output electrode CSSCo (92), a neutral electrode CSSCn (93) and asupply starter input electrode CSSCs (94).

CSSCac (91) is coupled to Vps (57), CSSCo (92) is a DC supply output,CSSCn is coupled to GND (60) and CSSCs is coupled to Vin+ (51).

Internally, the CSSC (90) contains a low power fast rectifier diode Dsc(95) having the anode coupled to CSSCac (91) and the cathode to CSSCo(92),), a small voltage bulk (47-220 uF) capacitor Csc (96) coupledacross CSSCo (92) and CSSCn (93), a zener diode DZsc (97) coupled withthe anode to CSSCn (93) and the cathode to CSSCo (92) and a startingresistor Rsc (98), coupled across CSSCs (94) and CSSo (92).

A coil Lsc (99) located in CPPC PCF IC (50), which receives electricalenergy from the inverter's oscillating coil L1 (61), supplies the CSSC(90) block with high frequency AC voltage, via Vps (57) and CSSCac (91)in respect to Vo− (53) and GND (60).

The CSSC (90) is a classic high frequency low power 16-20V DC voltagesupply for the controller circuit (optional), in which the AC voltageincoming from Lsc (99) is rectified by Dsc (95), filtrated by Csc (96)and limited by DZsp (97) at the CSSCO (92) output in respect to GND(60). The starting resistor Rsc (98) provides just the initial DCvoltage (low current) necessarily for the controller to startoscillating and then, Lsc (99) becomes the main source of the electricalenergy for the entire CSSC (90) block.

14.3 Design and Implementation

Al the above devices, except Rs (65) have been presented and describedin the previous embodiments. Rs (65) is a classic sense resistor whichprovides, at the VRs (59) output electrode, a variable voltage directproportional to M1 (63) momentary current amount.

14.3 Conclusions

This entire circuit has nothing special in respect to a classicboost-inverter used typically in the DC/DC conversion field, however itrepresents the “low cost” large signal supporting circuit, for a novelmethod of controlling the Power Factor, by the means of a Constant PulseProportional Current Method, in an AC/DC conversion circuit.

DESCRIPTION OF THE SSC EMBODIMENTS

The CPPC PFC-SSC Generic System

15.1 General Description

FIG. 15 illustrates a constant pulse proportional current power factorcorrection small signal generic embodiment CPPC PFC SSC, as acomplementary sub-circuit for the constant pulse proportional currentpower factor correction large signal circuit generic embodiment CPPC PFCLSC, in respect to the entire low cost high performances power factorcorrection system LCHPPFCS.

In other words, the CPPC PFC SSC GE (3) which will be described below,together with CPPC PFC LSC (2) which has been already described above(FIG. 14), complete the LCHPPFCS (1), the main subject of the presentinvention.

While the CPPC PFC method's high performances (PF>0.99, THD<5%) andsimplicity in implementation have been prove already (at the prototypelevel) for different configurations of the CPPC PFC LSC (50), the nextsubject of the present invention consist in a low cost solution,presented via the CPPC PFC SSC (3).

The generic embodiment presented in FIG. 15, includes a constant pulseproportional current power factor correction controller circuit CPPC PCFCC (100) and a controller's related circuit, CRC (110).

In order to achieve the above objective, and also to take full advantagefrom the fact that a CPPC System does not required an expensiveMultiplier sub-circuit (but just a simple “Constant Pulse”), the presentinvention's PFC controller circuit's design's target is to reaches thesimplicity of a PWM controller and of course, its 2-5 times lowermanufactory cost. Therefore, the present invention's PFC ControllerCircuit will be rather explained in respect to a classic PWM controllercircuit (i.e. UC384x) then to a PFC controller one (i.e. MC 33368),which is about six time more expensive.

15.2 The CPPC PFC-SSC Generic System Embodiment

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 15 113) a CPPC PFC SSCGE (3) is provided, representing a complementary system for the BoostCPPC PFC LSC GE (2) described above (FIG. 14 and comprising the CPPCPFC-CC (100) at the side of the CRC (110).

The figures suggest that the CPPC PFC-CC (100) improves the power factorin this circuit and the positions of the various terminals denote thefunction of each of them. In other words, in a CPPC PFC-CC (100)schematic diagram, the internal architecture and the positions of theterminals will illustrate, alone, the particular function of eachterminal. For the remainder of this description, the CPPC PFC-CC (100)may be referred to as a new controller circuit or NEWCTRL (100).

In this section, the presentation refers to the NEWCTRL (100) operatingmode, at the block schematic level only. Each of its internal functionalblocks' components will be further presented and described (FIG. 16 to25) as a sub-circuit of the NEWCTRL (100) and/or as a (several versions)independent system.

15.2 The Controller Circuit

The NEWCTRL (100), subject of this invention, is a Complex Mixed SignalSystem connected to the rest of the LCHPPFCS (1) via eight I/Oelectrodes: a feedback electrode FB (101) a compensation electrode(102), a non-linearity correction electrode NLC (103), a soft startelectrode SS (104), a ground electrode GND (105), a current limiterelectrode Ilim (106), a gate driving electrode DRV (107) and a supplyelectrode VCC (108).

A zero voltage internal connection 0v (109) serving as internal groundis connected to the GND (105) electrode.

15.3 The Controller's Related Circuit

Externally to the NEWCTRL (100), the CRS (110) includes a first feedbackresistor Rfb1 (111), a second feedback resistor Rfb2 (112), acompensation capacitor Cc (113), a first non linearity correctionresistor Rnlc1 (114), a second non linearity correction resistor Rvin2(115) and a soft start capacitor Css (116).

Rfb1 (111) is coupled to Vo+ (54) and to FB (101), Rfb2 (112) is coupledto FB (101) an to GND (60), Cs (113) is coupled between FB (101) andComp (102), Rvin1 (114) is coupled to Vin (51) and NLC (103), Rvin2 iscoupled to NLC (103) and GND (60), Css (116) is coupled to SS (104) andGND (60).

GND (105) is coupled to GND (60), Ilim (106) is coupled to Vrs (59), DRV(107) is coupled to DRVin (58), and VCC (108) is coupled to VDC+ (93).

The Vin (51), Vo+ (54), DRVin (58), Vrs (59) and VDC+ (93) electrodes aswell as any other reference numbers or parts which do not appear in FIG.15, belong to the NEWCTRL's (100) complementary sub-circuit, Boost CPPCPFC LSC GE (2), FIG. 14.

15.4 The Controller's Internal Circuit

Internally the NEWCTRL (100) contains an internal supply and protectionsblock ISP (150), a driver block DR (200), a voltage references blockVref (250), an analog reset pulse width modulator logic block AR-PWMLogic (300), a current limiter block CL (350), an analog resetoscillator block AR-OSC (400), a soft start block SS (450), a nonlinearity correction block NLC (500), an analog reset voltage rampdriver AR-VRD (550), a voltage error amplifier block VEA (600), avoltage limiter block VL (650), an analog reset comparator block ARC(700) and start enforcer block SE (750).

ISP (150) is a one signal/four supply terminals block, comprising anISPin+ (151) positive input supply electrode, an ISPin− (152) negativeinput supply electrode, a first ISPo1 (153) positive output supplyelectrode, a second ISPo2 (154) positive output supply electrode and anISPo3 (155) signal output.

ISPin+ (151) is coupled to the NEWCTRL (100) supply electrode VCC (108),ISPin− (152) is coupled to 0v (109), ISPo1 (153) is coupled to the Vref(250) block via a Vrin (254) electrode, ISPo2 (154) is coupled directlyto the DR (200) positive supply input and ISPo3 (155) is coupled to theAR-PWM Logic (300) block, via a first shut down SD1 (306) electrode.

DR (200) is a two signal terminals buffer, supplied from the ISPo2 (154)in respect to the internal ground 0v (109).

The DR (200) input is coupled to the AR-PWM-Logic (300) via a logicoutput Y (305) electrode and its output coupled to the NEWCTRL (100)driving output electrode, DRV (107).

Vref (250) is a five supply terminals voltage references provider block,comprising two input supply electrodes VRin+ (254), VRin− (255) andthree output supply electrodes Vref1 (251), Vref2 (252) and Vref3 (253).

VRin+ (254) is coupled to ISPo1 (153), VRin− (255) is coupled to 0v(109) and to the NEWCTRL (100) ground electrode, GND (105). Vref1 (251)supplies all the internal blocks except DR (200), Vref2 (252) provides areference voltage to the non-inverting input of VEA (600) and Vref3(253) provides a reference voltage to the inverting input of CL (350).

AR-PWM Logic (300) is a six signal terminals logic block, comprising aReset input electrode R (301), an Analog Reset Sync Pulse outputelectrode ARSP (302), a Set input electrode S (303), a second shut downinput electrode SD2 (304), an output Y (305) electrode and a second shutdown input electrode SD1 (306).

R (301) is coupled to the output of the ARC (700), ARSP (302) is coupledto the ARC (700) block via a CRS (701) input electrode and in somecircuit's configurations (optional) is coupled also to the AR-VRD (550)block via a VRDar (553) electrode, S (303) coupled to the AR-OSC (400)via a SET (401) output electrode, SD2 (304) is coupled to the CL (350)output, Y (305) is coupled to the input of DR (200) and SD1 (306) iscoupled to ISPo3 (153).

The CL (350) is a three signal terminals current limiter comparatorhaving its output coupled to AR-PWM Logic (300) via SD2 (304), itsinverting input coupled to Vref3 (253) and its non-inverting inputcoupled to the NEWCTRL (100) current limiter electrode Ilim (106).

The AR-OSC (400) is a four signal terminals oscillator block supplied byVre1 (251) in respect to 0v (109), comprising a SET (401) outputelectrode, a clock CLK (402) output electrode, a voltage ramp VR (403)output electrode and an analog reset voltage ramp ARVR ((404) electrode.

SET (401) is coupled to the AR-PWM Logic (300) block via S (303), CLK(402) is coupled in some circuit's configurations (optional) to theAR-VRD (550) block via a VRDar (553) electrode and one of VR (403) orARVR (404) is optionally coupled to AR-VRD (550) via an input electrodeVRDin (551).

The SS (450) is a two signal terminals soft start block supplied by theVref1 (251) in respect to the 0v (109), which has its input SSin (451)coupled to the NEWCTRL (100) soft start input electrode SS (104) and itsoutput SSo (452) coupled to the NEWCTRL (100) compensation inputelectrode Comp (102).

The NLC (500) is also a two signal terminals non linearity correctionblock supplied by the Vref1 (251) in respect to the 0v (109), which hasits input coupled to the NEWCTRL (100) non linearity correction inputelectrode NLC (103) and its output NLCo (502) coupled, in some circuit'sconfigurations (optional) to the NEWCTRL (100) compensation inputelectrode Comp (102) or, in other circuit's configurations (optional),to VRDo (554).

The AR-VDR (550) is a three signal terminals analog reset voltage rampdriver supplied by Vref1 (251) in respect to 0v (109) comprising avoltage ramp input VRin (551) electrode, a voltage ramp output electrodeVRo (554) electrode and a voltage ramp analog reset input VRar (553).

VRin (551) receives a voltage ramp signal from (optionally) VR (403) orARVR (404).

VRo (552) is coupled to the ARC (700) non-inverting input and in someother circuit's configurations the voltage ramp signal outputted by VRo(552) to the ARC (700) non-inverting input, may be resistively summedwith the signal incoming from Ilim (106) and/or the signal incoming fromNLC (500) via its output NLCo (502).

VRar (553) receives reset signal from (optionally) ARSP (302) or CLK(402).

The VEA (600) is a three signal terminals voltage error amplifier havingits inverting input coupled to the NEWCTRL (100) Feed-Back electrode FB(101), its non-inverting input coupled to the Vref2 (202) and its outputcoupled to the NEWCTRL (100) compensation input electrode Comp (102).

Reference is made herein to a VEA that includes various components invarious embodiments. In some embodiments, reference is made to ananalogic output or an sink analogic output. The output value of ananalogic output can range between a minimum and maximum value. On theother hand, a digital output can have only one of two states, such as alogical 0 and a logical 1 so that when a signal is high it isinterpreted as a logical 1 and when the signal falls below a certainvalue it is considered a logical 0.

The VL (650) is a two terminals voltage limiter block supplied by Vref1(251) in respect to 0v (109), which has its input VLin (651) coupled tothe VEA (600) output Comp (102) and its output coupled to the invertinginput of ARC (700).

The ARC (700) is a three signal terminals Analog Reset Comparator havingits output coupled to R (301), its inverting input coupled to theNEWCTRL (100) compensation input electrode Comp (102) and itsnon-inverting input coupled to VRo (554).

The SE (750) is a two signal terminals start enforcer block comprising aSEin (751) input electrode coupled to the Vref1 (251) and a SEo (752)output electrode coupled to the NEWCTRL (100) Feed-Back electrode FB(101).

Each of the above functional blocks' internal architecture will be indetails further described as a sub-circuit of the NEWCTRL (100) and/oras an independent system (FIG. 16 to 25).

15.5 Design and Implementation

The NEWCTRL (100) internal architecture is simple, following mostly astandard PWM structure and not a PFC one (no multiplier and relatedcircuit involved) being design to deliver a “Constant Pulse” inamplitude, frequency and duty/cycle to the gate of M1 (63), during atleast one semi-cycle of the Vac (10), in order for the entire LCHPPFCS(1) to provide high PFC performances (i.e. PF>0.99, THD<5%).

The “constant amplitude condition” is insured by the NEWCTRL's (100)supply voltage imputed to ISP (150) via VCC (108) which supposed to benot lower than 12v and limited to maxim 20V by ISP (150) before isdelivered to the DR (200).

In this range of voltage, M1 (63) works properly and is fully saturatedduring its ON switching time.

The “constant frequency condition” is insured by the NEWCTRL's (100)oscillator block AR-OSC (400), which in a standard design may vary0.5-2%, without affecting too much the entire PFC circuit performances.

For the “constant duty/cycle driving pulse during at least one Vac (10)semi-cycle condition”, several factors involving the Vac (10) amplitude,the M1 (63) circuit and the CL (40) circuit momentary currents, must beconsidered.

When the Vac (10) voltage is at its minim value (i.e. 90Vrms) and/or theCL (40) requests its maxim current (i.e. 0.5A for a 400V/200w output)the NEWCTRL's (100) driving pulse must reaches its maxim duty/cycle(i.e. 50-70%).

When the Vac (10) voltage is at its maxim value (i.e. 260Vrms) and/orthe CL (40) request its minim current (i.e. 0.05A for a 400V/20w output)the NEWCTRL's (100) driving pulse must reaches its minim duty/cycle(i.e. 0.1-10%).

When the Vac (10) voltage is higher than its maxim acceptable value(i.e. 280Vrms) and/or the CL (40) request no current (i.e. no load andVo>400V) the NEWCTRL's (100) driving pulse reaches 0 duty/cycle (nodriving pulse).

In this configuration of the NEWCTRL's (100) design, the driving pulse'smaxim duty/cycle is internally limited by the AR-OSC (400) or AR-VRD(550) blocks.

The momentary duty/cycle outputted at DRV (107) is a function of themomentary value of the voltage inputted at FB (101) and/or NLC (103) andor Ilim (106).

The current limiter input Ilim (!06) is mostly a protection electrodefor a too high current in M1 (63) circuit, so if the sense resistor Rs(64) is properly calibrated and the coil L1 (61) is not pushed out ofits linear range, the voltage inputted at Ilim (!06) does not modifysignificantly the driving pulse duty/cycle during one Vac (10)semi-cycle.

The non-linearity correction input NLC (103) is sensible only to high ACinput voltage or low Vout/Vin ratio, so if the resistors Rv1 (114) andRv2 (115) are properly calibrated, the voltage inputted at NLC (103)also does not modify significantly the driving pulse duty/cycle duringone Vac (10) semi-cycle.

The feedback electrode FB (101), which controls the duty/cycle inrespect to the Vo+ (54) momentary voltage also can not modifysignificantly the driving pulse duty/cycle during one Vac (10)semi-cycle because the bulk (100-470 uF) capacitor Cb (42) is able tokeep relatively constant the Vo+ (54) voltage during one Vac (10)semi-cycle and more than that, the compensation capacitor Cc (113) isspecifically calibrated (function of Cb (42) value) for preventing fastduty/cycle variations.

Therefore, the NEWCTRL's (100) is capable to deliver a “Constant Pulse”in amplitude, frequency and duty/cycle during, at least, one semi-cycleof low frequency high voltage generator Vac (10).

Also the NEWCTRL (100) has no special design requirements in respect toa classic low cost UC384x circuit.

The ISP (150), DR (200), Vref (250), SS (450), VEA (500) and VL (550)block can be design for reaching similarly specks to a classic UC3842(as an example).

The AR-OCS (400), AR-VRD (550), ARC (700) and AR-PWM Logic blocks'design is also pretty similar to the one applied for the OSC, VRD, C andPWM blocks existing in a classic US3842 (as an example), except some upgrades and/or adjustments that do not increase significantly the degreeof complexity and or cost/unit of the NEWCTRL (100) in respect to aclassic PWM controller. The main purpose of these up/grades implementedin the PWM circuit's section, is to obtain output driving pulses minimumduty/cycle about ten times shorter than typically, without using classicsolutions that include fast and expensive comparators and/or pulsedelaying circuits.

Finally, the novel blocks (in respect to UC384x) attached, such as NLC(502), SE (750) and CL (350) represent also very simple and inexpensiveaccessories, that substantially improve the NEWCTR (100) PFCperformances, without increasing significantly its design complexityand/or its manufacturing cost/unit feature.

Additionally, the NEWCTR (100) does not require a sophisticated and/orexpensive related circuit, so its implementation into a complete PFCSystem (including the LSC devices) is basically as simple as the onerequested by any classic UC384x series PWM controller.

The block by block description of this controller circuit, the apparatusembodiment as well as simulation results validated by bench prototypes'data, will be further presented and fully described, in addition to theabove NEWCTRL (100) description.

15.6 Conclusions

Because CPPC method allows for high PFC performances, requesting fromthe controller circuit nothing else but just a “constant pulse”, theNEWCTRL (100) degree of complexity and cost/unit can reach a suitablelevel, in the vicinity of a very low cost PWM controller circuit.

Obviously, the design of a controller circuit able to keep constant theduty/cycle driving output pulse during 8-10 uS, in a closed feedbackloop with the load's voltage, is not a major challenge, in the contextof the existing available technology.

The NEWCTRL (100) has no special design requirements in respect to aclassic low cost UC384x circuit.

As further embedded herein, the NEWCTRL (100) block schematic diagramsincludes three main sub-circuits:

-   1. The controller's Supply, Protection, References and Signal Output    sub-circuit including ISP (150), DR (200), Vref (300) and CL (350).-   2. The controller's Feedback, Corrections, Starter and Signal Input    sub-circuit including SS (450), NLC (500), VEA (600), CCS (650), VL    (651) and SE (750).

The controller's Analog Reset System Pulse Width Modulation sub-circuitincluding AR-PWM Logic (300), AR-OSC (400), AR-VRD (550) and ARC (700).

These sub-circuits (systems) will be further in detail described, at theblock and/or internal components level.

The ISP, DR, Vref and CL blocks

16.1 General Description

FIG. 16 illustrates the controller's Supply, Protection, References andOutput sub-circuit, comprising the ISP (150), DR (200), Vref (300) andCL (350) functional blocks.

16.2 The ISP block

ISP (150) is the internal supply and protection block comprisingcomparators with hysteresys, transistors and zener diodes in order tokeep within acceptable limits (typically 12-20v) the supply voltagedelivered internally to DR (200) and Vref (250) and also to be able toprovide a shut down pulse (logic 1) to AR-PWM Logic (300) in situationswhen the voltage incoming at VCC (108) is either too high (over 20V) ortoo low (less than 12V).

This ISP (150) block has no special requirements in respect to thesimilar ISP block included in the classic UC384x Circuit.

16.3 The DR block

DR (200) block is basically a high voltage (20v) buffer of the signalprovided by the PWM Logic (300) block at its Y (305) output. It must beable to drive, in good conditions a regularly MOSFET's gate, via DRV(107) output electrode, so a max 1Apk current (200 mA continuous) andabout 100 nS pulse raising time are the main challenging specs of thisbuffer.

This DR (200) block does not have also any special requirements inrespect to the similar DRV block included in the classic UC384x Circuit.

16.4 The Vref Block

Vref (250) is the functional block which provides at least three (Vref1,Vref2, Vref3) fix (stabile) supply and/or references voltages to all theother NEWCTRL (100) blocks and includes at least one high precision (1%preferable) Voltage Gap Reference.

Vref1 (251) delivers typically 5.0V, and besides its supply and highprecision reference attributes, its output provides a very low impedanceto ground (i.e. switch), during the time when stays at 0v level, factwhich allows for a fast discharge of any capacitor included in itscircuit (similarly to an automatically reset system).

This Vref (250) block also has no special requirements in respect to thesimilar DRV block included in the classic UC384x-PWM series.

16.5 The CL Block

CL (350) is a comparator which shuts down (keeps at low level) theAR-PWM Logic (300) driving signal output Y (305), when the voltage levelat Ilim (106) exceeds the Vref3 (253) voltage level.

In some lower cost circuit's versions, were the voltage incoming at Ilim(106) is resistively summed with VRDo (552) signal delivered to the ARC(700) non-inverting input, almost similarly performances could beobtained without this extra comparator CL (350) to be include in theinternal circuit of the NEWCTRL (100).

This current limiter comparator CL (350) does not exist in the classicUC384x Circuit; however its implementation does not significantly affectthe complexity degree level and/or the cost/unit amount of a newcontroller.

16.6 Design and Implementation

The above description of the ISP (150), DR (200), Vref (300) and CL(350) functional blocks, proves that basically there are no designand/or implementation issues for designing or “building in silicon” thiscontroller's specific sub-circuit.

16.7 Conclusions

For the above controller's sub-circuit, the performances/cost matterswill remain as attractive as the existing ones in respect to the UC3842series, because there is no need for modifying the above sub-circuit inrespect to classics.

The VEA, VL, SS, SE and NLC Blocks

17.1 General Description

FIG. 17 illustrates the controller's Feed-back, Corrections and StarterSignal Input sub-circuit, comprising the SS (450), NLC (500), VEA (600),VL (650) and SE (750) functional blocks.

17.2 The VEA Block

VEA (600), is a “current sink only” (open collector) operationalamplifier acting as a voltage error amplifier block which controls thevoltage level at Comp (102) in a classic “differential” manner withrespect to the voltage amounts at FB (101) and Vref2 (252).

The momentarily amount of voltage at Comp (102) determines, via ARC(700), AR-PWM Logic (300) and DR (200), the momentarily duty/cycle ofthe driving pulse outputted at DRV (107) in such a manner that, as highis Comp (102) voltage level, as large will be the percent amount of thedriving pulse's duty cycle.

The voltage amount at FB (101) is set by the two feedback resistors Rfb1(111) and RFB2 (112). The ratio of these to resistors is calculated toprovide a feedback voltage near Vref2 (252), respectively about 2.5V(typically) when the Vo+ (54) voltage reaches its pre-established maximvoltage (typically 380-420V).

As soon the Vo+ (54) voltage level goes beyond its pre-establishedamount, the voltage at FB (101) will exceed the Vref2 (252) voltageamount and VEA (600) will decreases the amount of voltage at Comp (102),fact that forces the output pulse's duty-cycle to decrease and finallythe Vo+ (54) voltage amount, also to decrease proportionally.

Since the driving pulse has a high frequency (30-500 kHz) and the load'sbulk capacitor Cb (42) value is relatively large (100-470 uF), the VEA(600) feedback circuit is able to keep easily the Vo+ (54) voltageamount in a +/−2% range, typically.

In order to keep the duty-cycle constant (i.e. Constant Pulse), thevalue of the compensation capacitor Cc (113) must be properly calibrated(large enough) for keeping the VEA (600) output at a relatively constantlevel at least one Vac (10) semi-cycle.

This VEA (600) does not have, also, any special requirements in respectto the similar VEA block included in the classic UC384x Circuit.

17.3 The VL Block

VL (650) comprises a constant current source CCSVL (653), a first zenerdiode ZVL1 (654), a first resistor RVL1 (655), a second resistor RVL2(656) and a second zener diode ZVL2 (657).

CCSVL (653) is coupled to VLin and the cathode of DZVL1 (654). Thecathode of DZVL1 (654) is coupled to VLo (652) via RVL1 (655). RVL2 andDZVL2 are coupled in parallel from VLo (652) to 0v (109). The cathode ofDZVL2 is coupled to VLo (652.

This “constant current source/voltage limiter circuit” delivers a 1 Vmax voltage amount at Comp (102), so the VEA (600) control of the Comp(102) voltage to be restricted within a 0-1 V range, in respect to 0v(109).

Also, for externally shut down and/or soft start purposes, the VL (650)block allows for a LOW Output (no pulse) at DRV (107) in the situationswhen Comp (102) is pushed down to a voltage level lower than 1 V(because DZVL1 threshold is about 1V).

CMCP PFC method, as well as any classic voltage mode PWM system,requests a pre-established driving pulse max duty cycle, for safetyreasons.

Since the Comp (102) max voltage is clamped at 1V, the entire system canbe design for a safe max 65% (typically) duty cycle output drivingpulse.

This VL (650) block does not have also any special requirements inrespect to the similar block and/or group of devices, included in theclassic UC384x Circuit.

17.4 The SS Block

SS (450) includes a PNP transistor Qss (453), a resistor Rss (454) and adiode Dss (455). The Qss has its collector coupled to 0v (109), itsemitter coupled to Comp (102) via SSo (452) and its base coupled to SS(104) via SSin (451) and to Vref1 (251) via Rss (454) in parallel to Dss(454). The anode of Dss (54) is coupled to the base of Qss (453).

When Vref1 (251) is “low” (0v), Comp (102) is low also because of theQss (453) and Rss (454). When Vref1 (251) switches “high” (5vtypically), the capacitor Css start charging via Rss (454), fact whichallows the Comp (102) voltage amount to increase slow, up to its maximumof 1V.

When the voltage at SS (104) exceeds 1v the base-emitter junction of Qss(453) is reverse polarized (very large impedance), so after thisthreshold, the SS (450) devices are not included anymore in the Comp(102) circuit.

When Vref1 (251) switches back “low” (0v), Css (116) is discharged(reset) via Dss (455) and the low impedance to GND (switch) of the Vref1(251) electrode.

In other words, the SS (450) block forces a slow increase of the Comp(102) voltage for a short time (proportional to Css and Rss) only,during each supplying transit time. A few milliseconds after the systemis supplied with DC voltage, Qss (453) disconnects the SS (450) systemfrom the Comp (102) circuit.

Since the output driving pulse's duty/cycle is proportional to the Comp(102) voltage amount, the SS (450) circuit forces a safe graduatedincreasing duty/cycle, in order to avoid a too high current amount inthe M1 (63) circuit.

This SS (450) block is not included inside of a classic UC384x Circuit;however its implementation does not significantly affect the complexitydegree level and/or the cost/unit amount of a new controller.

17.5 The SE Block

SE (750) comprises a resistor Rse (753) and a diode Dse (754).

Dse (754) has its cathode coupled to the SSin (751) block's inputterminal and its anode are coupled to the SSo (753) block's outputterminal, via Rse (753).

The purpose of this attached functional block is to assure the circuit“start process” in some critical situations, respectively when theNEWCTRL (100) is (A) included in a self-supply system (such as SC (90),FIG. 14), (B) the input ac voltage Vac (10) is above 200Vrms and (C) theresistive load RI (41) has a very high value or is initiallydisconnected from the circuit (very low or even zero load current).

In order for Rsc (97) to not dissipate to much heat (typically less than0.5w) its circuit's current amount is calculated to be just enough (1-2mA) for charging Csc (98) above 16v for starting the NEWCTRL (100)oscillations, and immediately after start, a much larger currentincoming from Lsc (95), is design to provide the controller sustainingcurrent (100-200 mA). In other words, Lps (95) is actually the ac supplygenerator for the NEWCTRL (100).

The amount of the ac voltage provided by Lps (95) is direct proportionalto the current in L1 (61), which is direct proportional to theduty/cycle of the pulse delivered to M1 (63) gate, via DRV (107).

The duty/cycle of the driving pulse decreases down to zero (no pulse)when the voltage at FB (101) exceeds the Vref2 (252) voltage (2.5vtypically).

When Vac (10) amount is over 200Vrms, the Vo+ (54) voltage increase fastand also the FB (101) voltage amount increases proportionally near itsmax pre-established level (2.5v) before VCC (108) supply input reaches16V, and also before Vref1 (251) switches “high” and releases Comp (102)from its extra circuit (i.e. SS (450)) to the internal ground.

Because of that, the compensation capacitor Cc (113) is chargedinitially with a high amount of voltage value, via the Qss (453) circuitof the SS (450) block, before the controller even starts deliveringdriving pulses.

As a negatively result, Cc (113) acts as an unneeded secondary DC source(its value is about 1 uF typically) which may increases the FB (101)voltage amount (up to over 2.5v) and decrease proportionally (down to 0%eventually) the driving pulse duty/cycle.

In order to avoid this situation, SE (750) keeps FB (101) and the Cc(113) voltage amount at a lower level via Rse (753, Dse (754) and Vref1(251) until Rsc (97) charges Csc (98) and VCC (108) supply input exceedsthe necessarily 16v threshold for start.

As soon Vref (251) switches “high” (and the driving pulses start beingdelivered) the Dss (754) is reverse polarized and SE (750) does notaffect anymore the FB (101) circuit.

This SE (750) block does not exist in the classic UC384x Circuit;however its implementation does not significantly affect the complexitydegree level and/or the cost/unit amount of a new controller.

17.6 The NLC Block

In FIG. 17 shows a first NLC (500) embodiment version, as subject ofthis invention, comprising just a simple resistor Rnlc (504) coupledacross NLCin (501) which is connected to the NEWCTRL (100) non linearitycontrol input NLC (103) and NLCo (502), which is connected, in parallelto VRDO (552) for modulating the voltage ramp signal delivered to thenon-inverting input of the ARC (700).

As further embodied herein a Non Linearity Correction system NLC (500),able to decrease the controller's driving pulses' duty/cycle, in a BoostCPPC PFC System, while the AC generator's momentary voltage amountexceeds half of the output load's DC voltage, contains one resistor Rnlc(504) connected from NLC (103) to the non-inverting input of the ARC(700).

The Rnlc1 (504) designed function, in this NLC (500) embodimentconfiguration, is to ad to the voltage ramp signal delivered by VRDo(552) to the non inverting input of ARC (700), a fraction of the Vin+(51) signal delivered via Rnlc1 (114), Rnlc2 (115) and the NEWCTRL (100)input non linearity correction input NLC (103).

As has been explained during the previous description of the CPPC PCFBoost circuit, the NLC (500) is necessarily only when the Vac (10) peakvoltage reaches high values, in the vicinity of the Vo+ (54) amount(Vo/Vin<1.5).

As long as in a boost configuration, the Vo+ (54) level is 1.5-2 timeshigher than the Vin (51) peak voltage, the system can reach a PF>0.99without involving the NLC (500) correction system.

In other words, in the situation when Vo+ (54) amount is set for about400 VDC, the CPPC-PCF Boost System does not requires a NLC (500) blockin Japan, were the standard AC voltage amounts is 90Vrms (120Vpk), doesnot requires also a NLC (500) block in USA were the standard AC voltageamount is 120Vrms (170Vpk), however it does require a NLC (500) block inEurope, were the standard AC voltage amount is 240Vrms (340Vpk).

17.7 Design and Implementation

The above description of the SS (450), NLC (500), VEA (600), VL (650)and SE (750) functional blocks, proves that basically there are nodesign and/or implementation issues for designing or “building insilicon” this controller's specific sub-circuit.

Even three extra functional blocks have been incorporated in respect toa classic PWM controller architecture (such as SS (450), NLC (500) andSE (750), functional blocks) as the devices level description shows,only one extra transistor, two diodes and two resistors are actuallyattached to a standard PWM circuit. These parts represent a very smallpercent in respect to the rest of the circuit's exiting internaldevices.

17.7 Conclusions

For the above controller's sub-circuit, the performances/cost mattersstill remain as attractive as the existing ones in respect to the UC3842series. The above attached sub-circuit complexity and cost areinsignificant factors in respect to a classic UC 384x controllercircuit.

The NLC Block

18.1 General Description

NLC (500) is a non linearity correction circuit which can be embodied inseveral different configurations according to the main designconsideration, such as cost, accuracy of control, simplicity, lesscontroller's pin-out count, etc.

This block represent another simple solution of resolving the maininconvenient of the boost CPPC PFC System, respectively a non linearincreasing of the AC generator current when the peak input voltageexceeds half of the output DC voltage.

FIG. 18 illustrates three more embodiment versions, of the NLC (500)block.

18.2 The 2^(nd) NLC Block Embodiment

FIG. 18A shows a different configuration of the NLC (500) System, assubject of this invention, implemented in a three signal I/O electrodessuch as NLCin (501), NLCo (502) and NLCref (503).

In this configuration, NLC (500) System comprises internally, asink-only (open collector) operational amplifier OAn (505), a firstresistor Rn1 (506), a second resistor Rn2 (507) and a capacitor Cn(508).

The OAn (505) has its output coupled to NLCo (502), its non-invertinginput coupled to NLCref (503) and its inverting input coupled to NLC in(501) via Rn1 (506). Rn2 (507) and Cn (508) are both, in parallel,coupled between the inverting input and the output of OAn (505), as aclassic OPAM's negative feedback.

18.3 Design and Implementation

As further embodied herein a Non Linearity Correction system NLC (500),able to decrease the controller's driving pulses' duty/cycle, in a BoostCPPC PFC System, while the AC generator's momentary voltage amountexceeds half of the output load's DC voltage, contains one operationalamplifier OAn (505), two resistors Rn1 (506), Rn2 (507) and a capacitorCn (508) included as a functional block NLC (500) of the NEWCTRL (100).

A fraction of the Vin+ (51) full rectified sine wave signal inputted atNLC (103) electrode is differentially amplified by OAn (505) whichcontrols the Comp (102) voltage, in parallel to VEA (600). The Comp(102) voltage modulation rate is determined by Rn1 (506)-Rn2 (507) ratioin respect to the difference of the voltage inputted at NLCref (503) andNLCin (501).

Since the fraction of the Vin+ (51) signal is applied to the invertinginput of OAn (505), when Vin+ (51) reaches its peak, the Comp (102)voltage reaches its minim value and implicitly, the controller's drivingpulses' duty/cycle decreases proportionally.

By using the FB (101) voltage, as reference at NLCref (503), the NLC(500) block may act as a protection circuit also, by decreasing theduty/cycle down to 0% (no pulse) in dangerous transit situations whenVin+ (51) peak voltage may reach an equal or even higher voltage amountthan Vo+ (54).

In some this particularly design versions, NLCref (503) may eliminatethe needs for a soft start block.

This NLC (500) configuration provides a much better accuracy of controland flexibility in design; however it is more expensive than theprevious one.

18.4 The 3^(rd) NLC Block Embodiment

FIG. 18B shows a different configuration of the NLC (500) System, assubject of this invention, implemented into controller's related circuitCPPC PFC CRC (110), respectively into the FB (101)-Comp (102) circuit.

In this configuration, NLC (500) System comprises two resistors Rn3(511) and Rn4 (512) attached to the existing Rfb1 (111), Rfb2 (112) andCc (113) feedback and compensation circuit of the NEWCTRL (100).

Rn3 (511) is connected from Vin+ (51) to FB, Rn4 (512) is coupled fromFB (101) to the middle connection of the Rfb1 (111) and Rfb2 (112), theother terminal of Rfb1 is coupled to Vo+ (54), the other terminal ofRfb2 is coupled to 0v (109) and Cc (113) is coupled from the middleconnection of the Rfb1 (111) and Rfb2 (112) to Comp (102).

18.5 Design and Implementation

As further embodied herein a Non Linearity Correction system NLC (500),able to decrease the controller's driving pulses' duty/cycle, in a BoostCPPC PFC System, while the AC generator's momentary voltage amountexceeds half of the output load's DC voltage, contains two resistors Rn3(511) and Rn4 (512), attached to the controller related circuit'sfeedback/compensation sub-circuit.

Rn3 (511) modulates the FB (101) feedback voltage incoming from Vo+ (54)with a fraction of the Vin+ (41) full rectified sine wave signal, sowhen Vin+ (41) reaches its peak, the FB (101) voltage reaches its maxvalue and implicitly, the controller's driving pulses' duty/cycledecreases proportionally.

The Rn4 (512) stops Cc (113) to integrate this low amplitude NLCmodulation signal.

This above circuit uses VEA (600) as NLC amplifier, via a simple tworesistors circuit implementation.

This implementation can be very useful for a different 8 pinconfiguration of the NEWCTRL (100), in which the NLC (103) inputelectrode can be replaced with a reference voltage output electrode oran external control oscillator input electrode.

18.6 The 4^(th) NLC Block Embodiment

FIG. 18C shows a final different configuration of the NLC (500) System,as subject of this invention, implemented into controller's relatedcircuit CPPC PFC CRC (110), respectively into the FB (101) sub-circuitwhich does not use a large value compensating capacitor.

In this configuration, NLC (500) System comprises two resistors Rn5(513) and Rn6 (514) attached to the existing Rfb1 (111), Rfb2 (112)circuit of the NEWCTRL (100).

The new feedback circuit contains a first feedback resistor Rfb1 (111),Rfb2 (112) coupled from Vo+ (54) to FB (101), a second feedback resistorRfb2 (112) coupled from FB (101) to 0v (109) via Rn6 (516) and afeedback capacitor Cfb (122) coupled in parallel to Rfb2 (112). Rn5(515) is coupled from the middle connection of Rn6 (516) and Rfb2 (112)to Vin+ (51).

18.7 Design and Implementation

As further embodied herein a Non Linearity Correction system NLC (500),able to decrease the controller's driving pulses' duty/cycle, in a BoostCPPC PFC System, while the AC generator's momentary voltage amountexceeds half of the output load's DC voltage, contains two resistors Rn5(513) and Rn6 (514) attached to the controller related circuit'sfeedback sub-circuit.

Rn5 (511) modulates the FB (101) feedback voltage incoming from Vo+ (54)with a fraction of the Vin+ (41) full rectified sine wave signal, sowhen Vin+ (41) reaches its peak, the FB (101) voltage reaches its maxvalue and implicitly, the controller's driving pulses' duty/cycledecreases proportionally.

The Rn4 (512) stops Cfb (122) to integrate this low amplitude NLCmodulation signal.

This above circuit uses VEA (600) as NLC amplifier, via a simple tworesistors circuit implementation.

This implementation can be very useful for a different 8 pinconfiguration of the NEWCTRL (100), in which the NLC (103) inputelectrode and the Comp (102) electrode can be replaced with a referencevoltage output electrode, with an external control oscillator inputelectrode or with any other needed I/O electrode.

18.6 Conclusions

This NLC (500) block does not exist in the classic UC384x Circuit;however its implementation does not significantly affect the complexitydegree level and/or the cost/unit amount of a new controller, especiallyin its “passive versions” (resistors only).

In situations when a much accuracy of control is needed, an extraoperational amplifier has to be attached, fact which increases the totalcost accordingly.

However, further descriptions (apparatus embodiment) prove that highperformances, such as PF=0.999 and THD<1%, can be reached by using apassive NLC version, more specific, just a $0.001 resistor.

The Pulse Width Modulation Sub-circuit

19.1 General Presentation

In view of the fact that the main object of the present invention refersto a “Low Cost High Performances PFC System” and a current mode PWMcontroller circuit cost is 2-5 times lower than the classic PFCcontroller circuit, one of this invention's goals is to use the cheapestPWM circuit version (such as the one used in UC384x series), but also toprovide a PF>0.99 and THD<5%.

The main inconvenient sensed in classic low cost, current mode PWMcontrollers circuits (such as UC3842 series) consist in their incapacityof providing short ON time driving pulses (typically Ton>1 uS), for somereasons explained above. These short ON time pulses are absolutelynecessarily in a Voltage Mode PWM Controller System, as well as, in aHigh Performances PFC System.

In order to reach these above “high performances”, one or morefunctional blocks included in a low cost PWM sub-circuit must be modifyaccordingly however, in such a manner that finally, the cost/unit toremain about the same.

As a further subject of the present invention, an Analog Reset SystemPWM sub-circuit is provided, in order to up-grade and/or to eliminatesome of the classic mixed signal circuits' inconvenient. This novelsystem does not requires fast comparators and/or expensive delaycircuits, but a reset sync-pulse only (Analog Reset), provided by the“OSC” or “PWM Logic” block and applied to the “VRD” or “C” block.Therefore typically, only one or two of these above four blocks need ARSimplementation. The other two or three blocks may remain unchanged, inrespect to a classic PWM circuit.

FIG. 19 shows comparatively, a classic PWM circuit in the section A,versus four different versions of Analog Reset PWM circuits, presentedin the sections B to E.

Since there are several different configuration of connecting the AR-PWMSub-circuit blocks and each of them has some advantages against theothers, the Analog Reset method has been implemented in all of thesefour above classic functional blocks, for providing the necessarilydesign's flexibility in respect to the performances/cost issues.

In this chapter, the AR-PWM Sub-circuit will be described at the blocklevel only.

Each of the above AR blocks internal architecture will be furtherdescribed in detail, (down to the component level) in the next chapters.For the reminder of this description to the Analog Reset Pulse WidthModulation System may be referred as AR-PWM (3).

19.2 The Classic PWM Circuit

Generically, a PWM circuit is a mixed signal system able to deliver avariable duty/cycle square wave (digital) driving signal, in a ratiodirect proportional to the momentary voltage amount comparatively sensedby its (analog) inputs, respectively a variable feedback signal and asynchronized voltage ramp signal.

Typically the synchronized voltage signal is provided by a squarewave/voltage ramp wave's oscillator (generator) circuit, which alsoprovides setting (sync) pulses to a PWM Logic circuit, attached forallowing not more than one output driving pulse per each oscillatorcycle.

FIG. 19A shows a classic voltage mode PWM circuit comprising fourfunctional blocks, respectively a two signal outputs (SET) and (VR)oscillator (OSC) block, a one input (VRDin)—one output (VRDO) voltageramp driver (VRD) block, a two inputs—one output comparator (C) blockand a two inputs (R, S) one output (Y) pulse width modulation logic (PWMLogic) block.

FIG. 28 illustrates the shape of the most significant PWM circuit'ssignals delivered in FIG. 19 section A (classic PWM) vs. section B(AR-PWM), respectively “V(SET)”, “V(VR)”, “V(Comp)”, “V(VR-A)”,“V(RES-A)”, and “V(DRV-A)”.

Accordingly, the output signal “V(DRV-A) duty/cycle ratio outputted bythe PWM Logic circuit is direct proportional to the momentary voltageamount sensed by the comparator (C) inverting input “V(Comp)” in respectto the synchronized voltage ramp signal “V(VR-A)” incoming via a voltageramp driver (VRD) from a square wave/voltage ramp wave's oscillator(OSC) and inputted at the comparator's non-inverting input.

The OSC block delivers a “V(SET)” signal via its output SET to the Sinput of PWM Logic block and also delivers a “V(VR)” signal via its VRoutput to the VRDin input of the VRD block. The VRD block delivers a“V(VR-A)” signal to the non-inverting input of the comparator C, versusa decay DC voltage “V(Comp)” applied to the inverting input of thecomparator C. The comparator C output delivers a “V(RES-A)” signal tothe PWM Logic R input. The PWM Logic output Y delivers a “V(DRV-A)”signal in accordance to the Truth Table shown at FIG. 6H 3.

As FIG. 28 section D shows and in accordance to the PWM Logic TruthTable, the “V(DRV-A)” pulse starts immediately when the “V(SET)” pulsefalls to its LOW logic level and ends when either “V(RES-A)” and/or“V(SET)” reaches the HIGH logic level.

Accordingly, the “V(DRV-A)” pulses ON time decrease proportional to the“V(Comp)” decay in respect to “V(VR-A)” (FIG. 28, section B), howeverthe “V(DRV-A)” signal disappears after just a few pulses, before itreaches a needed 1% duty/cycle ratio (i.e 0.2 uS from 20 uS, @ 50 kHz).

This inconvenient occurs because an important condition of the classicPWM Logic circuit Truth Table, does not allows the output pulse to startwhen the “V(SET)” pulse falls LOW, if “V(RES-A)” is not already in LOWlogic state. When a low speed (and also low cost) comparator is used,and “V(Comp)” level reaches the lower edge of “V(VR-A)” signal,“V(RES-A)” reaches its LOW logic level too late (after “V(SET)” isalready LOW) and the shortest ON time pulse remains typically in a rangeof 1-4 uS, in a classic UC384x circuit.

The following embodiments of the present inventions represent a seriesof new and low cost solutions that resolved this above importantinconvenient, without using expensive sub-circuits such as fastercomparators, mono-stabile and/or delaying circuits.

Also these novel solutions allow for a fix operating frequency, featurethat allays represents a significant “plus” in the PFC circuits' design.

19.3 The 1^(st) ARS PWM Sub-Circuit Embodiment

In FIG. 19B an ARS-PWM (3) sub-circuit is provided, as subject of thisinvention, comprising four functional blocks, respectively a four signaloutputs SET (401), CLK (402), VR (403) and ARVR (404) analog resetoscillator AR-OSC (400) block, a two inputs VRDin (551), DARin (553)—oneoutput VRDo (552) analog reset voltage ramp driver AR-VRD (550) block, atwo inputs—one output classic comparator C (745) block and a two inputs(R, S) one output (Y) classic pulse width modulation logic PWM Logic(345) block.

The ARVR (404) output of the AR-OSC (400) block is not used in thisARS-PWM (3) sub-circuit (system) version.

AS FIG. 19B shows, in this system configuration, only the AR-OSC (400)and AR-VRD (550) blocks request the implementation of the Analog Resetmethod.

The AR-OSC (400) block's internal architecture's versions and TimingDiagrams are shown in FIG. 20A-D and will be presented in detail atChapter 22: The AR-OSC Block Circuit Embodiments (page XX).

The AR-VRD (550) block's internal architecture versions are shown inFIG. 21A-B and will be presented in detail at Chapter 21: The AR-VRDBlock Circuit Embodiments (page XX).

The other two blocks such as C (745) and PWM Logic (345) may have aclassic internal architecture involving, eventually, no extra cost fordesign and implementation in respect to a standard UC384x circuit.

FIG. 28 illustrates the shape of the most significant PWM circuit'ssignals delivered in FIG. 19 section B (AR-PWM) vs. section A (classicPWM), respectively “V(SET)”, “V(VR)”, “V(Comp)”, “V(VR-B)”, “V(RES-B)”,and “V(DRV-B)”.

The AR-OSC (400) block delivers a “V(SET)” signal via its output SET(401) to the S (302) input of PWM Logic (345) block, a “V(CLK) signalvia its CLK (402) output to the DARin (553) input of AR-VRD (550) andalso delivers a “V(VR)” signal via its VR (403) output to the VRDin(351) input of the AR-VRD (550) block. The AR-VRD (550) block delivers a“V(VR-B)” signal to the non-inverting input of the comparator C, versusa decay DC voltage “V(Comp)” applied to the inverting input of thecomparator C. The comparator C output delivers a “V(RES-B)” signal tothe PWM Logic (395) R (301) input. The PWM Logic (395) output Y (305)delivers a “V(DRV-B)” driving signal in accordance to the Truth Tableshown at FIG. 6H 3.

The classic low speed (low cost) current mode PWM circuit's inconvenient(i.e. in voltage mode PWM, the duty/cycle cannot be forced down to 1% orless) does not occur in this situation because the important conditionof the classic PWM Logic circuit Truth Table (i.e. for Y=1, R must beLOW before S switches LOW) has been satisfied by implementing the AnalogReset Method in this particularly PWM circuit.

FIG. 28 section A shows that the “V(CLK)” signal is identical but inopposite faze to the “V(SET)” signal, and the “V(VR) signal increaseslinearly when “V(SET)” is LOW and decreases linearly when “V(SET)” isHIGH.

FIG. 28 section B shows that unlike “V(VR-A)”, the “V(VR-B)” signalapplied to the C (745) non-inverting input, is rapidly pushed near 0v by“V(CLK)” as soon “V(SET)” switches HIGH and then is kept at LOW levelduring the entire “V(SET)” pulse ON time.

Also unlike “V(VR-A)” which is crossing slow the “V(Comp)” decay signalapplied to the C (745) inverting input, the “V(VR-B)” voltage leveldrops much faster under the “V(Comp)” voltage level, forcing an earlieroutput switching (typically 4 uS@100 kHz running frequency). Since avery low speed (low cost) classic comparator does not need more than 2-3uS to switch to a firm LOW state, a “V(SET)” pulse ON time of 4 uS ismore than enough for a safe Analog Reset accomplishment.

FIG. 28 section C shows that, because the “V(VR-B)” signal reaches alower voltage level than the “V(Comp)” momentary voltage amount a fewmicroseconds earlier than the “V(VR-A)” signal, implicitly the“V(RES-B)” signal reaches its LOW logic state a few microseconds beforethe “V(RES-A)” signal.

FIG. 28 section E shows that in accordance to the PWM Logic Truth Table,the “V(DRV-B)” pulse starts immediately when the “V(SET)” pulse falls toits LOW logic level (0) and ends when either “V(RES-B)” and/or “V(SET)”switch to the HIGH logic level (1). Accordingly, the “V(DRV-B)” pulsesON time decrease proportional to the “V(Comp)” decay in respect to“V(VR-B)” and the “V(DRV-B)” signal is delivered until it reaches aratio even lower than 1% duty/cycle and start decreasing in amplitude.

Despite the PWM comparator C (745) low speed, if the “V(VR-B)” pulse isforced in LOW state before “V(SET)” switch LOW (i.e. the “V(SET)” pulseON time is equal or larger than the PWM comparator's output “fallingtime”), than the shortest “V(DRB-B)” driving pulse (AR-PWM System) ismuch shorter than the “V(DRB-A)” shortest driving pulse (Classic PWMSystem, FIG. 28 section D), going finally as short as the digitaldevices switching speed allows. When the pulse width is forced shorterthan the digital buffer's total switching time (raise time plus falltime), then of course the output driving pulse start decreasing inamplitude.

In other words, after the implementation of the Analog Reset Method, aMixed Signal PWM System is able to run at the limits of its digitaldevices switching speed (typically 50-100 nS), even the analog PWMcomparator switching speed is 10-20 times lower (1-2 uS).

FIG. 34A-H illustrates comparatively, a complete Computer Simulationproject, including the schematic diagrams, voltage graphs, partsattributes, general specs, and simulation results of an AR-PWM Systemvs. a classic PWM System, described in detail In Chapter 19.8: Designand Implementation.

19.5 The 2^(nd) ARS PWM Sub-Circuit Embodiment

In FIG. 19C another ARS-PWM (3) sub-circuit (system) version isprovided, as subject of this invention, comprising four functionalblocks, respectively a classic two signal outputs SET (401) and VR (403)oscillator OSC (445) block, a classic one input VRDin (551)—one outputVRDo (552) voltage ramp driver VRD (595) block, a three inputs,inverting, non-inverting and CRS (701)—one output analog resetcomparator ARC (700) block and a classic two inputs (R, S) one output(Y) pulse width modulation logic PWM Logic (345) block.

AS FIG. 19C shows, in this system configuration, only the ARC (700)block requests the implementation of the Analog Reset method.

The ARC (700) block's internal architecture versions are shown in FIG.22A-B and will be presented in detail at Chapter 22: The ARC BlockCircuit Embodiments.

The other three blocks such as OSC (445), VRD (595) and PWM Logic (345)may have a classic internal architecture, involving eventually no extracost for design and implementation, in respect to a standard UC384xcircuit.

FIG. 28A-E illustrates the shape of the most significant PWM circuit'ssignals delivered in FIG. 19C, respectively “V(SET)”, “V(VR)”,“V(Comp)”, “V(VR-A)”, “V(RES-B)” and “V(DRV-B)”.

The OSC (445) block delivers a “V(SET)” signal via its output SET (401)simultaneously to the S (302) input of PWM Logic (345) block and to theARC (700) comparator reset switch input CRS (701). Also the OSC (445)block delivers a “V(VR)” signal via its VR (403) output to the VRDin(351) input of the VRD (595) block. The VRD (595) block delivers a“V(VR-A)” signal to the non-inverting input of the analog resetcomparator ARC (700), versus a decay DC voltage “V(Comp)” applied to theinverting input of the ARC (700). The ARC (700) output delivers a“V(RES-B)” signal to the PWM Logic (395) R (301) input. The PWM Logic(395) output Y (305) delivers a “V(DRV-B)” driving signal in accordanceto the Truth Table shown at FIG. 6H 3.

Despite the fact that in this sub-circuit version a “V(VR-A)” signal isinputted to the non-inverting input of the analog reset comparator ARC(700), versus a decay DC voltage “V(Comp)” applied to its invertinginput, the “V(SET)” signal inputted at CRS (701) keeps the ARC (700)output in LOW state (reset) during the entire “V(SET)” pulse ON time.

The classic low speed (low cost) current mode PWM circuit's inconvenient(i.e. in voltage mode PWM, the duty/cycle cannot be forced down to 1% orless) does not occur in this situation because the important conditionof the classic PWM Logic circuit Truth Table (i.e. for Y=1, R must beLOW before S switches LOW) has been satisfied by applying the AnalogReset method (via CRS (701) directly to the ARC (700), so a “V(RES-B)”signal (switching LOW earlier than a “V(RES-A)” signal) is outputted tothe reset input R(301) of the PWM Logic (345) block.

The system presented in FIG. 19C works similar to the previous onepresented in FIG. 19B and has the same very good performances (Tonmin<40 nS, D/C<0.5%).

This particularly embodiment advantages in respect to the other AR-PWMsub-circuits embodiments configurations, will be discussed in detailbelow.

19.6 The 3^(rd) ARS PWM Sub-Circuit Embodiment

In FIG. 19D another ARS-PWM (3) sub-circuit (system) embodiment versionis provided, as subject of this invention, comprising four functionalblocks, respectively a classic two signal outputs SET (401) and VR (403)oscillator OSC (445) block, a classic one input VRDin (551)—one outputVRDo (552) voltage ramp driver VRD (595) block, a three inputs,inverting, non-inverting and CRS (701)—one output analog resetcomparator ARC(700) block and a analog reset four inputs R (301), S(303), SD1 (304), SD2 (306), two outputs ARSP (302), Y (305) analogreset pulse width modulation logic AR-PWM Logic (300) block.

The SD1 (304) and SD2 (306) inputs of the AR-PWM Logic (300) block arenot used in this sub-circuit embodiment.

AS FIG. 19D shows, in this system configuration, only the ARC (700) andthe AR-PWM Logic blocks request the implementation of the Analog Resetmethod.

The ARC (700) block's internal architecture versions are shown in FIG.22A-B and will be presented in detail at Chapter 22: The ARC BlockCircuit Embodiments (page XX).

The AR-PWM Logic (300) block's internal architecture versions are shownin FIG. 23A-B and will be presented in detail at Chapter 23: The AR-PWMLogic Block Circuit Embodiments (page XX).

The other two blocks such as OSC (445), VRD (595) may have a classicinternal architecture, involving eventually no extra cost for design andimplementation, in respect to a standard UC384x circuit.

FIG. 28A-E illustrates the shape of the most significant PWM circuit'ssignals delivered in FIG. 19C, respectively “V(SET)”, “V(VR)”,“V(Comp)”, “V(VR-A)”, “V(RES-B)” and “V(DRV-B)”.

The OSC (445) block delivers a “V(SET)” signal via its output SET (401)to the S (302) input of PWM Logic (345) block and a “V(VR)” signal viaits VR (403) output to the VRDin (351) input of the VRD (595) block. TheVRD (595) block delivers a “V(VR-A)” signal to the non-inverting inputof the analog reset comparator ARC (700), versus a decay DC voltage“V(Comp)” applied to the inverting input of the ARC (700). The ARC (700)output delivers a “V(RES-B)” signal to the PWM Logic (395) R (301)input. The PWM Logic (300) delivers Y (305) delivers a “V(DRV-B)”driving signal in accordance to the Truth Table shown at FIG. 6H 3. Thesame “V(DRV-B)” signal is delivered to the CRS (701) of the ARC (700)via its ARSP (302) output.

Despite the fact that in this sub-circuit version a “V(VR-A)” signal isinputted to the non-inverting input of the analog reset comparator ARC(700), versus a decay DC voltage “V(Comp)” applied to its invertinginput, the “V(DRV-B)” signal inputted at CRS (701) keeps the ARC (700)output in LOW state (reset) during the entire “V(SET)” pulse ON time(according to the classic PWM Logic circuit Truth Table when S=1 thenY=0).

The classic low speed (low cost) current mode PWM circuit's inconvenient(i.e. in voltage mode PWM, the duty/cycle cannot be forced down to 1% orless) does not occur in this situation because the important conditionof the classic PWM Logic circuit Truth Table (i.e. for Y=1, R must beLOW before S switches LOW) has been satisfied by applying the AnalogReset method (via CRS (701) directly to the ARC (700), so a “V(RES-B)”signal (switching LOW earlier than a “V(RES-A)” signal) is outputted tothe reset input R(301) of the PWM Logic (345) block.

The system presented in FIG. 19C works similar to the previous onepresented in FIG. 19B and has the same very good performances (Tonmin<40 nS, D/C<0.5%).

This particularly embodiment advantages in respect to the other AR-PWMsub-circuits embodiments configurations, will be discussed in detailbelow.

19.7 The 4^(th) ARS PWM Sub-Circuit Embodiment

In FIG. 19E another ARS-PWM (3) sub-circuit (system) embodiment versionis provided, as subject of this invention, comprising three functionalblocks, respectively a four signal outputs SET (401), CLK (402), VR(403) and ARVR (404) analog reset oscillator AR-OSC (400) block aclassic two inputs—one output comparator C (745) block and a classic twoinputs (R, S)—one output (Y) pulse width modulation logic PWM Logic(345) block.

The CLK (402) and VR (403) outputs of the AR-OSC (400) block are notused in this sub-circuit configuration.

AS FIG. 19E shows, in this system configuration, only the AR-OSC (400)block requests the implementation of the Analog Reset method.

The AR-OSC (400) block's internal architecture's versions and TimingDiagrams are shown in FIG. 20A-D and will be presented in detail atChapter 22: The AR-OSC Block Circuit Embodiments (page XX).

The other two blocks such as C (745) and PWM Logic (345) may have aclassic internal architecture, involving eventually no extra cost fordesign and implementation, in respect to a standard UC384x circuit.

FIG. 28A-E illustrates the shape of the most significant PWM circuit'ssignals delivered in FIG. 19C, respectively “V(SET)”, “V(Comp)”,“V(VR-B)”, “V(RES-B)” and “V(DRV-B)”.

The AR-OSC (400) block delivers a “V(SET)” signal via its output SET(401) to the S (302) input of PWM Logic (345) block and a “V(VR-B)”signal via its ARVR (404) output directly to the non-inverting input ofthe comparator C (700), versus a decay DC voltage “V(Comp)” applied tothe inverting input of the ARC (745). The comparator C (745) outputdelivers a “V(RES-B)” signal to the reset input R (301) of the PWM Logic(345). The PWM Logic (345) output Y (305) delivers a “V(DRV-B)” drivingsignal in accordance to the Truth Table shown at FIG. 6H 3.

In this sub-circuit configuration embodiment, the AR-OSC (400) blockdelivers an Analog Reset “V(VR-B)” signal directly to the C (745)non-inverting input versus a decay DC voltage “V(Comp)” applied to itsinverting input. By adjusting properly the “V(Comp)” amplitude, there isno more need for a voltage ramp driver block. The “V(VR-B)” signal issynchronized with “V(SET)” and is able to reset periodically the PWMcomparator C (745) and keep its output in LOW state during the entire“V(SET)” pulse ON time.

The classic low speed (low cost) current mode PWM circuit's inconvenient(i.e. in voltage mode PWM, the duty/cycle cannot be forced down to 1% orless) does not occur in this situation because the important conditionof the classic PWM Logic circuit Truth Table (ie. for Y=1, R must be LOWbefore S switches LOW) has been satisfied by implementing the AnalogReset Method into the AR-OSC (400) block, which forces the comparator C(745) to deliver a “V(RES-B)” signal (switching LOW earlier than a“V(RES-A)” signal) to the reset input R(301) of the PWM Logic (345)block.

The system presented in FIG. 19C works similar to the previous onepresented in FIG. 19B and has the same very good performances (Tonmin<40 nS, D/C<0.5%).

This particularly embodiment advantages in respect to the other AR-PWMsub-circuits embodiments configurations, will be discussed in detailbelow.

FIGS. 20, 21, 22 and 23 show the internal architecture of all the AR-PWM(3) functional blocks, including the implementation of the Analog ResetSystem for each.

19.8 Design and Implementation

The implementation of the Analog Reset System method in a mixed signalPWM circuit is simple and provides considerable flexibility in designand parts selection.

The main features (i.e. PF and THD) of PCF System rely on the PWM Systemimplemented in the Controller Circuit. For high performances this PWMSystem must provide a duty/cycle percent lower than 1%, without usingfast comparators or expensive delay circuits.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, stability vs. temperature variations and even cost price, beforethe decision of building a bench prototype is taken.

The following Computer Simulation requested about 15 minutes (computertime) and it is by itself an evidence of the ARS implementation anddesign's simplicity.

FIG. 33A-H illustrates comparatively, a complete Computer Simulationproject, including the schematic diagrams, voltage graphs, partsattributes, general specs, and simulation results of a Classic PWMSystem (similarly to the one presented in FIG. 19A) versus an AR-PWMSystem (similarly to the one presented in FIG. 19B). The main purposesof running this Computer Simulation Project were to reach a briefestimation of the Analog Reset Method implementation's performances in asimple and low cost PWM circuit. A brief image of the timing diagrams,wave forms accuracy vs. noise, as well as the main parts attributes(including size and cost), were also important design targets of thissimulation.

The Simulations' results presented below are self-explanatory: V(CLK)V(SET) minV(DRV) - PWM (Ton- (Ton- RT FT Comparator ON Circuit uS) uS)(uS) (uS) (LM) (uS) Classic 15 5 0.1 0.1 139 2.5 (A) AR- 15 5 0.1 0.1139 0.04 PWM (B)

As the above chart shows, in similarly conditions of V(CLK), V(SET),oscillator raise and fall time RT, FT and using the same (low cost)SPICE model comparator LM 139, the AR-PWM is able to deliver a drivingpulse about 60 times shorter than classic's and also a min duty/cycle of0.5%.

As a brief guide of this design (simulation) project, the most relevantitems are:

FIG. 33A presents comparatively two almost identical PWM circuit'sschematic diagrams sharing the same VR, SET and comp signals.

The only difference consist in three extra parts attached at section B(AR-PWM) respectively Dar, Cdar and Rvrd.

The CLK signal “resets” the Q1B (and implicitly the comparator C/U1B)during the SET signal ON time (i.e. CLK signal OFF time) via the diodeDar.

The capacitor Cdar integrates a short spike (noise) created when CLKsignal gets HIGH because of the Dar parasite capacitance.

The Rvrd keeps the U1-B non-inverting input at a minim level slightlyhigher than 0, for avoiding the situation of “non-stop” driving pulse,which may happened if the “Comp” signal does not reach a firm 0 voltage(i.e. GND) level.

FIG. 33B shows the parts list and the pulse generators main specs.

FIG. 33C shows a comparative (ARS vs. Classic PWM) generic view (2 mSsimulation time) of the voltage against time graphs for the ten maincircuits' signals such as: V(CLK), V(SET), V(VR), V(VR-A), V(VR-B),V(Comp), V(RES-A), V(RES-B), V(DRV-A) and V(DRV-B).

As a generic observation, for the section A (Classic PWM) circuit, theoutput driving pulse signal V(DRV-A) ends after about 1.4 mS (the red ordark grey signal) however for the section B (ARS PWM) circuit the outputdriving pulse signal V(DRV-B), keeps going in shorter and shorter pulsesalmost the entire 2 mS simulation's time (the green or light greysignal).

FIG. 33D shows in detail the first 200 uS (zoomed) of the FIG. 34Btiming diagrams chart. The following aspects are more noteworthy:

-   1. The V(CLK) and V(SET) signals are identical but in opposite    phase, so the other signals synchronization can be referred to    V(SET) only.-   2. The voltage ramp V(VR) signal increases slowly during V(SET) OFF    time and decreases faster, down to its initial level, during V(SET)    ON time.-   3. V(Comp) decrease slowly at the top of V(VR-A) and V(VR-B) signal.-   4. V(VR-B) is identical to V(VR-A) during the OFF time of V(SET),    however V(VR-B) is pushed near 0v (reset) during the ON time of    V(SET).-   5. The V(RES-A) pulses appears a little bit before V(RES-B) pulses.-   6. The V(DRV-A) and V(DRV-B) pulses start when V(SET) switches OFF    (LOW logic) and end when V(SET) switches ON (HIGH logic) if there    are no V(RES-A) or respectively no V(RES-B) pulses.-   7. V(DRV-A) ends when V(RES-A) switches HIGH and V(DRV-B) ends    V(RES-B) switches HIGH.-   8. When V(Comp) level reaches the top of V(VR-A) and V(VR-B)    signals, V(DRV-A) and V(DRV-B) output driving pulses reach their    maximum duty cycle, pre-established by V(CLK).

FIG. 33E shows the same initial ten timing diagrams signals in respectto the final two V(DRV-A) pulses.

The last V(DRV-A) pulse starting at, simulation time, 1.40 mS isvalidated by the fact that V(RES-A) reaches already 0v level when V(SET)switches LOW logic.

The very next V(DRV-A) pulse that was supposed to be delivered at,simulation time, 1.42 mS has been not validated because V(RES-A) wasstill at HIGH level when V(SET) switches LOW logic.

However V(DRV-B) next pulse has been validated because, by the means ofan Analog Reset Method, V(RES-B) was pushed down to zero a relativelylong time before V(SET) switches LOW logic.

FIG. 33F shows the same initial ten timing diagrams signals in respectto the last V(DRV-A) pulse.

Its lasting time is about 2.5 uS which means more than 10% minimumduty/cycle from a total pulse period of 20 uS. Both, the ON time and theminimum duty/cycle ratio are way too large for a good accuracy ofcontrol and implicitly for a high performances PFC or PWM circuit. Forhigh performances, an ON time and a duty/cycle pulse about 10 timesshorter are firmly required. FIG. 33G shows the same initial ten timingdiagrams signals in respect to the final two V(DRV-B) pulses.

The last V(DRV-A) pulse starting at, simulation time, 1.92 mS isvalidated by the fact that V(RES-B) reaches already 0v level when V(SET)switches LOW logic, as a result of the Analog Reset Method.

As FIG. 34G shows the V(DRV-B) last pulse is much shorter than shows theV(DRV-A) last pulse, for the same 20 uS pulse period. Obviously thepulse duty/cycle ratio of this pulse will be proportional to its shorterON time.

FIG. 33H shows the same initial ten timing diagrams signals in respectto the last V(DRV-B) pulse.

Its lasting time is less than 0.04 uS which means less than 0.5% minimumduty/cycle from a total pulse period of 20 uS. Both, the ON time and theminimum duty/cycle ratio are, this time, in a good range for a highperformances PFC and/or PWM circuit.

As the above data show, the Analog Reset method can be easilyimplemented without increasing significantly the cost of a classic PWMcircuit.

All the above items complete the basic design for the VD-Boost Systemversion of the CPPC PFC LSC (50), which is an important subject of thepresent invention.

The Bench Data fully confirm the performances of the CPPC Method appliedto a Boost CPPC PFC System and its Computer Simulation components'attributes.

19.9 Conclusions

By applying the Analog Reset Method in a Mixed Signal Circuit, theoperating rate of the entire system is improved up to the digitaldevices switching speed.

By applying the Analog Reset Method to a classic, low speed/low cost PWM50 kHz circuit, the minimum driving pulse time can be reduced about 60times (0.04 uS vs. 2.5 uS) and the minimum duty/cycle can be reducedabout 20 times (0.5% vs. 10%), without a significant increase of thetotal cost.

Four different AR-PWM (3) System Embodiments have been provided, assubjects of these inventions. Each of them has some particularlyadvantages in respect to the implementation's cost, complexity ofdesign, accuracy of control and versatility and compatibility ofoperations.

The 1^(st) AR-PWM (3) System Embodiment configuration presented in FIG.19B can be very easy implemented, however it request three extra parts,a CLK extra signal from the oscillator and a SET signal having a minimum3 uS (for a low speed comparator) ON time.

The 2^(nd) AR-PWM (3) System Embodiment presented in FIG. 19C is able touse three classic functional blocks, however the ARC (700) comparatorblock requests significant modifications and a SET signal having aminimum 3 uS (for a low speed comparator) ON time.

The 3rd AR-PWM (3) System Embodiment presented in FIG. 19D does notrequest a SET signal having a minimum 3 uS (for a low speed comparator)ON time however it still include an ARC (700) comparator blockcomprising a fast and low noise switch.

The 4^(th) AR-PWM (3) System Embodiment presented in FIG. 19D isapparently the ideal one, having just three functional blocks, howeverit request a very good calibration of the Comp signal in respect to theoscillators' analog reset voltage ramp signal.

Each designer may chose a one version of this above AR-PWM (3)sub-circuits or a combination of them, in order to reach the bestperformances/cost compromise.

The AR-OSC Block

20.1 General Description

AR-OSC (400), the system's oscillator block is supplied by Vref1 (251)in respect to the internal ground 0v (109) and has four signal outputelectrodes: a SET (401) electrode, a CLK (402) electrode, a voltage rampVR (403) electrode and an analog resetting voltage ramp ARVR (404)electrode.

Internally, the AR-OSC (400) contains transistors, comparators and logicgates connected in very different architectures.

FIG. 20A-C shows three different AR-OSC versions, able to deliver (eachof them) at SET (401), CLK (402), VR (403) and ARVR (404) the samespecific output pulses, having the shape and synchronization inaccordance to the waves illustrated in the Timing Diagrams graph, FIG.20D.

20.2 The 1^(st) Oscillator Embodiment

FIG. 20A shows a first analog reset oscillator AR-OSC (400) embodimentversion, subject of this invention, comprising a two transistorsa-stabile (multi-vibrator) system which includes a first transistor Qa1(405), a second transistor Qa2 (406), a first capacitor Ca1 (407), asecond capacitor Ca2 (408), a first resistor Ra1 (409), a secondresistor Ra2 (410), a third resistor Ra3 (411), a fourth resistor Ra4(412), a first inverter buffer IA1 (413), a second inverting buffer IA2(414), a charging resistor Rch (415), a voltage ramp capacitor Cvr(416), a discharge diode Ddch (417), a discharge resistor Rdch (418) anda last capacitor Cd (419).

Qa1 has its collector coupled to Vref1 (251) via Ra1 (409), its basecoupled to Vref1 (251) via Ra2 (410) and its emitter coupled directly to0v (109). Qa2 has its collector coupled to Vref1 (251) via Ra4 (412),its base coupled to Vref1 (251) via Ra3 (411) and its emitter coupleddirectly to 0v (109). Ca1 is coupled between the collector of Qa1 (405)and the base of Qa2 (406). Ca2 is coupled between the collector of Qa2(406) and the base of Qa1 (405). IA1 has its input coupled to thecollector of Qa2 and its output coupled directly to CLK (402) and viaIA2 (414) to SET (401). Ddch (417) cathode is coupled to the output ofIA1 (413) and its anode is coupled directly to ARVR (404), to VR (403)via Rdch (418) and to 0v (109) via Cd (419). Rch is coupled from VR(403) to Vref1 (251) and Cvr (416) is coupled between VR (403) and 0v(109).

As further embedded herein, Qa1 (405), Qa2 (406), Ca1 (407), Ca2 (408),Ra1 (409), Ra2 (410), Ra3 (411) and Ra4 (412) establish a classicmulti-vibrator square wave generator, providing a clock signal at CLK(402), via IA1 (413) and a “clock-bar” (reversed phase) signal at SET(401).

During each oscillating cycle, Cvr (416) is charged by Rch (415) anddischarged by IA1 (413) via Ddch (417) and Rdch (418), providing asynchronized voltage ramp signal at VR (403) and also a synchronizedanalog reset voltage ramp signal at ARVR (404).

As FIG. 20D shows the ARVR signal is pushed near 0v (reset) during theentire time of the SET signal ON time.

The Ddch (417) voltage threshold (0.4-0.7v) helps for keeping the ARVRsignal's lower edge to a convenient level above 0v, in order to avoid a“non-stop” NEWCTRL (100) output driving pulse, since in a real circuitsituation, the “V(Comp)” signal's lower level, applied to the invertinginput of the PWM comparator is not 0v, but 0.1-0.2v.

The capacitor Cd (419) integrates a short spike (noise) created when CLKsignal gets HIGH because of the Ddch (417) parasite capacitance.

All the four signals' shapes outputted by AR-OSC are shown in FIG. 20D.

20.3 The 2^(nd) Oscillator Embodiment

FIG. 20B shows a second analog reset oscillator AR-OSC (400) embodimentversion, subject of this invention, containing a comparator withhysteresis ST1 (421), an inverting buffer INV (422), a discharge diodeDth (423), a discharge resistor Rdch (424), a noise rejection capacitorCd (425), a voltage ramp capacitor Cvr (426) and a charging resistor(427).

ST1 (421) has its input coupled directly to VR (403), via Rch (427) toVref1 (251) and via and via Cvr (426) to 0v (109). The ST1 (421) outputis coupled directly to CLK (402) and via the inverting buffer INV (422)to SET (401). Rdch has its anode coupled to ARVR (404) and its cathodecoupled to CLK (402). Rdch (423) is coupled between VR (403) and ARVR(404). Cd (425) is coupled between ARVR (404) and 0v (109).

As further embedded herein, the comparator with hysteresis ST1 (421)together with the capacitor Cvr (426), the charging resistor Rch (427),the discharging resistor Rdch (424) and the discharging diode Ddch(423), establish a classic square wave generator, providing a clocksignal at CLK (402), a voltage ramp signal at VR (403) and an analogreset voltage ramp signal at ARVR (404).

During each oscillating cycle, Cvr (426) is charged by Rch (427) anddischarged by ST1 (421) via Ddch (423) and Rdch (424), providing asynchronized voltage ramp signal at VR (403) and also a synchronizedanalog reset voltage ramp signal at ARVR (404).

As FIG. 20D shows the ARVR signal is pushed near 0v (reset) during theentire time of the SET signal ON time. Via INV1 (422) a “CLK-bar”(reversed phase) or SET signal is delivered at SET (401).

The Ddch (423) voltage threshold (0.4-0.7v) helps for keeping the ARVRsignal's lower edge to a convenient level above 0v, in order to avoid a“non-stop” NEWCTRL (100) output driving pulse, since in a real circuitsituation, the “V(Comp)” signal's lower level, applied to the invertinginput of the PWM comparator is not 0v, but 0.1-0.2v.

The capacitor Cd (425) integrates a short spike (noise) created when CLKsignal gets HIGH because of the Ddch (423) parasite capacitance.

All the four signals' shapes outputted by AR-OSC are shown in FIG. 20D.

20.4 The 3^(rd) Oscillator Embodiment

FIG. 20C shows a third analog reset oscillator AR-OSC (400) embodimentversion, subject of this invention, containing a first oscillatingcomparator OC1 (431), a second oscillating comparator OC2 (432), a firsttwo inputs NOR logic gate NOR1 (433), a second two inputs NOR logic gateNOR2 (434), a high level voltage reference source Voh (435), a lowvoltage reference source Vol (436), a base resistor Rqb (437), a NPNdischarging transistor Qdch (438), a threshold diode Dth (439), adischarging resistor (440), a charging resistor Rch (441) and a voltageramp capacitor Cvr (442).

OC1 (431) has its non-inverting coupled to VR (403), its inverting inputcoupled to the positive pole of Voh (435) and the negative pole of Voh(435) is coupled to 0v (109).

NOR1 (433) has one input coupled to the OC1 (431) output, the otherinput coupled to SET (401) and its output coupled to CLK (402).

OC2 (432) has its inverting coupled to VR (403), its non-inverting inputcoupled to the positive pole of Vol (436) and the negative pole of Voh(436) is coupled to 0v (109).

NOR2 (434) has one input coupled to the OC2 (432) output, the otherinput coupled to CLK (402) and its output coupled to SET (401).

Rqb (437) is coupled from SET (401) to the base of Qdch (438). The Qdch(438) emitter is coupled to 0v (109) and its collector to the cathode ofDth (439). The anode of Dth (439) is coupled directly to ARVR (404) andvia Rdch (440) to VR (403).

Rch (441) is coupled from Vref1 (251) to VR (403) and Cvr (442) iscoupled from VR (403) to 0v (109).

As further embedded herein, the two oscillating comparators OC1 (431),OC2 (432) together with the two NOR logic gates NOR1 (433), NOR2 (434)coupled in a RS Latch logic circuit and also together with a high levelvoltage reference source Voh (435), a low voltage reference source Vol(436), a base resistor Rqb (437), a NPN discharging transistor Qdch(438), a discharging resistor (440), a charging resistor Rch (441) and avoltage ramp capacitor Cvr (442) establish a classic square wavegenerator, providing a clock signal at CLK (402), a setting signal atSET (401) a voltage ramp signal at VR (403) and an analog reset voltageramp signal at ARVR (404), act as typical mixed signal oscillator block.

The DTh (439) voltage threshold (0.4-0.7v) helps for keeping the ARVRsignal's lower edge to a convenient level above 0v, in order to avoid a“non-stop” NEWCTRL (100) output driving pulse, since in a real circuitsituation, the “V(Comp)” signal's lower level, applied to the invertinginput of the PWM comparator is not 0v, but 0.1-0.2v.

The noise rejection capacitor included in the previous two AR-OSC (400)versions for integrating the short spike (noise) created when CLK signalgets HIGH because of the Ddch (423) parasite capacitance is not neededin this circuit, since Cvr (442) has a relatively high value (typically1-4.7 nF) and Rdch (440) a relatively small value (0.4-3K).

During each oscillating cycle, Cvr (442) is charged by Rch (441) anddischarged by Qdch (438) via Dth (423) and Rdch (440), providing asynchronized voltage ramp signal at VR (403) and also a synchronizedanalog reset voltage ramp signal at ARVR (404).

As FIG. 20D shows the ARVR signal is pushed near 0v (reset) during theentire time of the setting signal ON time, delivered at SET (401). Aclock signal is obtained at CLK (402) without including any extra parts,in respect to a classic mixed signal oscillator.

All the four signals' shapes outputted by AR-OSC are shown in FIG. 20D.

20.5 Design and Implementation

The implementation of the Analog Reset Method in a classic oscillatorcircuit is simple and provides considerable flexibility in design andparts selection and does not request expensive extra parts for obtainingit specific signals such as ARVR and/or CLK.

The Computer Simulations are now indispensable design tools for a goodand fast estimation of a new circuit's parts attributes, performances,size, stability vs. temperature variations and even cost price, beforethe decision of building a bench prototype is taken.

The following Computer Simulation requested about 5 minutes (computertime) and it is by itself an evidence of the Analog Reset Methodimplementation design's simplicity.

FIG. 34A-D illustrates, a complete Computer Simulation project,including the schematic diagrams, voltage graphs, parts attributes,general specs, and simulation results of a Analog Reset OscillatorCircuit (similarly to the one presented in FIG. 20C). The main purposesof running this Computer Simulation Project were to reach a briefestimation of the Analog Reset Method implementation's performances in asimple and low cost oscillator circuit. A brief image of the ARVR signalin respect to all the other synchronized timing diagrams, wave formsaccuracy vs. noise, as well as the main parts attributes (including sizeand cost), were also important design targets of this simulation.

As a brief guide of this design (simulation) project, the most relevantitems are:

FIG. 34A shows an AR-OSC circuit schematic diagram, similar to the onepresented in FIG. 20C (page 117).

FIG. 34B shows the parts and the voltage references' attributes.

FIG. 34C shows a generic view (200 uS simulation time) of the voltageagainst time graphs for the four main signals such as: V(CLK), V(SET),V(VR), and V(ARVR).

FIG. 34D shows in detail (2 cycles), comparatively, V(CLK) vs. V(SET)and V(VR) vs. V(ARVR).

V(CLK) is actually V(SET) in opposite phase and V(ARVR) signal isidentical to V(VR) one, during V(SET) pulse OFF time, however V(ARVR)signal is kept near 0v the entire V(SET) pulse ON time.

All the above items complete the basic design for the AR-OSC (400) mosttypical version of the NEWCTRL (100), which is an important subject ofthe present invention.

20.6 Conclusions

As the above data show, the Analog Reset Method can be easilyimplemented without increasing significantly the cost of a classicoscillator circuit.

The Bench Prototypes fully confirm the performances of the Analog ResetMethod applied to a classic Mixed Signal oscillator circuit and itscomputer simulation components' attributes.

The AR-VRD Block

21.1 General Description

AR-VRD (550), the system's voltage ramp driver block is also supplied byVref1 (251) in respect to the internal ground 0v (109) and has threesignal I/O electrodes: a voltage ramp driver VRDin (551) inputelectrode, a voltage ramp driver VRDo (552) output electrode, and driveranalog reset DARin (553) input electrode.

21.2 The 1^(st) AR-VRD Embodiment

FIG. 20A shows a first analog reset voltage ramp driver AR-VRD (550)embodiment version, as subject of this invention, containing a sink-onlyoperational amplifier VRD1 (554), a first driver resistor Rd1 (555), asecond driving resistor Rd2 (556), a three terminals (one for control)analog reset switch ARsw (557), and a reset minim voltage level sourceRMVLs (558).

VRD1 (554), supplied by Vref1 (251) in respect to 0v (109) has itsnon-inverting coupled to VRDin (551) and its inverting input togetherwith its output coupled directly to VRDo (552), via Rd (555) coupled toVref1 (251) and via Rd2 (556) coupled to 0v (109). RMVLs (558) has itsnegative pole coupled to 0v (109) and its positive pole coupled to VRDo(552) via the ARsw (557) switch. The ARsw (557) controlling input iscoupled to DARin (553).

As further embedded herein, VRD1 (554) acts as a current buffer (voltagefollower) for the voltage ramp signal incoming at VRDin (551), in orderto protect the oscillator block for eventually distortions and/oralterations of its generating signal.

The resistive divider Rd1 (555), Rd2 (556) adjusts to convenient lowerlever the voltage ramp signal outputted trough VRDo (552).

The analog reset switch ARsw (557) transforms the Voltage Ramp (VR)signal into an Analog Reset Voltage Ramp (ARVR) signal, respectively bythe means of a synchronized controlling signal inputted at DARin (553),the analog reset switch ARsw (557) keeps the output signal voltage levelnear 0v (reset) during the time when the voltage ramp input signaldecrease from it maximum value to its initial value only (see the OSCTiming Diagrams FIG. 20 D.

The reset minim voltage level source RMVLs (558) helps for maintainingthe ARVR signal's lower edge at a convenient level above 0v, in order toavoid a “non-stop” NEWCTRL (100) output driving pulse, since in a realcircuit situation, the “V(Comp)” signal's lower level, applied to theinverting input of the PWM comparator is not a firm 0v, but about0.1-0.2v.

21.3 The 2^(nd) AR-VRD Embodiment

FIG. 20A shows a second analog reset voltage ramp driver AR-VRD (550)embodiment version, as subject of this invention, containing a PNPtransistor VRD2 (561), a first voltage ramp resistor Rvr1 (564),), asecond voltage ramp resistor Rvr1 (562),), a third voltage ramp resistorRvr1 (563), a fourth voltage ramp resistor Rvr1 (567), an analog resetdiode Dar (565) and a noise rejection capacitor Cdar (566).

VRD2 (561) has collector coupled to Vref1 (251), its base coupled toVRDin (551) via Rvr1 (564) and its emitter coupled to VRDo (552) viaRvr2 (562). Rvr3 (563) is coupled from VRDo (552) to 0v (109), Rvr4 iscoupled from Vref1 (251) to VRDo (552), Dar (565) is coupled with itsanode to the VRD2 (561) base and its cathode to DARin (553).

Cdar (566) is coupled from 0v (109) to the anode of Dar (565).

As further embedded herein, VRD2 (561) acts as a current buffer (voltagefollower) for the voltage ramp signal incoming at VRDin (551), in orderto protect the oscillator block for eventually distortions and/oralterations of its generating signal.

The resistive divider Rvr2 (562), Rvr3 (563) adjusts to convenient lowerlever the voltage ramp signal outputted trough VRDO (552).

The analog reset diode Dar (565) transforms the Voltage Ramp (VR) signalinto an Analog Reset Voltage Ramp (ARVR) signal, respectively by themeans of a synchronized controlling signal inputted at DARin (553), theanalog reset diode Dar (565) keeps VRD2 (561) base and implicitly theoutput signal voltage level near 0v (reset) during the time when thevoltage ramp input signal decrease from it maximum value to its initialvalue only (see the OSC Timing Diagrams FIG. 20D.

Rvr4 (567) helps for maintaining the ARVR signal's lower edge outputtedat VRDo (552) at a convenient level above 0v, in order to avoid a“non-stop” NEWCTRL (100) output driving pulse, since in a real circuitsituation, the “V(Comp)” signal's lower level, applied to the invertinginput of the PWM comparator is not a firm 0v, but about 0.1-0.2v.

The capacitor Cdar (566) integrates a short spike (noise) created whenthe signal inputted at DARin (553) gets HIGH because of the Dar (565)parasite capacitance.

21.4 Design and Implementation

At section (chapter) 19.8 a complete PWM System computer simulationdesign project, including a AR-VRD circuit similar to the oneillustrated in FIG. 21B, has been fully described.

21.5 Conclusions

The implementation of the Analog Reset Method in a classic Voltage RampDriver circuit is simple, provides considerable flexibility in designand parts selection and does not request expensive extra parts forobtaining its specific signals such as ARVR.

The ARC block

22.1 General Description

AR-VRD (700), the system's analog reset comparator block is supplied byVref1 (251) in respect to the internal ground 0v (109) and comprises,besides the classic three signal I/O electrodes such as an invertinginput, a non-inverting input and an output, an extra specific comparatoranalog reset input CARin (701) electrode.

22.2 The 1^(st) ARC Embodiment

FIG. 22A shows a first analog reset comparator ARC (700) embodimentversion, as subject of this invention, containing a classic comparator C(702) and a double switch Sw1-Sw2 (703) sub-circuit.

The comparator C (702), supplied by Vref1 (251) in respect to 0v (109)has its inverting input coupled externally to Comp (102) outputelectrode of the NEWCTRL (100) and its output coupled externally to thereset R (301) input electrode of the ARS-PWM Logic (300) block.

The non-inverting input is connected to the switching block (703) insuch a manner that can be alternatively coupled externally to the VRDo(552) output electrode of the VRD (550) block via Sw1, or internallycoupled to 0v (109) via Sw2. Sw1 and Sw2 are always in opposite state,respectively when Sw1 is closed then Sw2 is open and vice versa.

CARin (701), which controls the Sw1 and Sw2 momentary condition, can bealternatively coupled externally to the ARSP (302) output electrode ofthe AR-PWM Logic (300) block, or to the SET (401) oscillator block'soutput electrode.

As further embedded herein, the ARC (700) acts as a synchronized analogreset comparator with respect to the voltage ramp signal incoming fromVRDo (552), the feedback signal incoming from Comp (102) and the squarewave pulse inputted at CARin (701) in order to maintain the ARC (700)output (i.e. R (301) signal voltage level near 0v (reset) during thetime when the voltage ramp input signal decrease from it maximum valueto its initial value, only.

The switches block (703) has to work in such a manner that when thevoltage ramp input signal increase from its initial value to its maximumvalue, Sw1 is CLOSED and Sw2 is OPEN and when the voltage ramp inputsignal decrease from it maximum value to its initial value, then SW1 isOPEN and Sw2 is CLOSED.

22.3 The 2^(nd) ARC Embodiment

FIG. 22B shows a second analog reset comparator ARC (700) embodimentversion, as subject of this invention, containing only a three inputscomparator C (704).

The three inputs comparator C (704), supplied by Vref1 (251) in respectto 0v (109) has its inverting input coupled externally to Comp (102)output electrode of the NEWCTRL (100) and its output coupled externallyto the reset R (301) input electrode of the ARS-PWM Logic (300) block.

The third input is connected CARin (701), which can be alternativelycoupled externally, to the ARSP (302) output electrode of the AR-PWMLogic (300) block, or to the SET (401) oscillator block's outputelectrode.

As further embedded herein, the ARC (700) acts as a synchronized analogreset comparator with respect to the voltage ramp signal incoming fromVRDo (552), the feedback signal incoming from Comp (102) and the squarewave pulse inputted at CARin (701) in order to maintain the ARC (700)output (i.e. R (301) signal voltage level near 0v (reset) during thetime when the voltage ramp input signal decrease from it maximum valueto its initial value, only.

The C (704) comparator's third input polarity must be choused in such amanner that during the time when the voltage ramp input signal decreasefrom it maximum value to its initial value, the C (704) output to be inLOW state. In other words, the polarity of the third input is choused inrespect to the polarity of the sync pulses incoming from SET (401) orARSP (302) to the analog reset CARin (701) input.

22.4 Design and Implementation

The ARC sub-circuit can be easily designed and implemented in a mixedsignal circuit, by following a classic “gated amplifier” model,frequently used in mixers and/or “Sample and Hold” circuits. Computer'ssimulations and bench prototypes prove that there is no need for a fast(and expensive) switching operation, however there is a need of a “lownoise” switching operation, in order to achieve a high performanceAnalog Reset Comparator sub-circuit.

22.5 Conclusions

The ARC is a novel circuit, however its implementation is simple,provides considerable flexibility in design and parts selection and doesnot request expensive extra parts for obtaining a high performancesmixed signal circuit.

The AR-PWM Logic Block

23.1 General Presentation

AR-PWM Logic (300), the system's pulse with modulation logic block isalso supplied by Vref1 (251) in respect to the internal ground 0v (109)and has four signal output electrodes: a reset R (301) input electrode,a analog reset sync pulse ARSP (302) output electrode, a set S (303)input electrode, a first shut down SD1 (304) protection input electrode,a logic Y (305) output electrode and a second shut down SD2 (306)protection input electrode.

23.2 The 1^(st) AR-PWM Logic block Embodiment

FIG. 23A shows a first analog reset pulse with modulation logic AR-PWMLogic (300) embodiment version, as subject of this invention, containinga four inputs one output NOR3 (307) logic gate, a two inputs one outputRS logic Latch (308) which uses only its Q-bar (inverted) output, and acurrent buffer BUFo (309).

The four inputs NOR3 (307), has its first input coupled to SD2 (306),its second input coupled to the Q (bar) output of the Latch (308), itsthird input coupled to the Latch (308) S input and its fourth inputcoupled SD1 (304). The NOR3 (307) output is coupled directly to ARSP(302) and via BUFo (309) to Y (305). The Latch (308) has its reset Rinput coupled to R (301) and its set S input coupled to S (303).

As further embedded herein, the AR-PWM Logic (300) block, provides anoutput signal at Y (305) function of the momentary voltage levelprovided to its inputs electrodes, in accordance to the truth tableshown in FIG. 6 h 3, as long as the voltage amount inputted to its twoprotection inputs SD1 (304) and SD2 (306), remains at the LOW logiclevel. If at least one of this protection inputs is switches HIGH, thanthe Y (305) output switches LOW.

For obtaining the necessarily analog reset sync pulse outputted at ARSP(302) there is no need for extra parts included into AR-PWM Logic (300),but just an extra connection wire from the NOR3 (307) output to the ARSP(302) electrode. The same driving signal delivered trough Y (305) can bedelivered to the ARC (700) block trough the ARSP (302) electrode.

23.3 The 2^(nd) AR-PWM Logic Bloc Embodiment

FIG. 23B shows a second analog reset pulse with modulation logic AR-PWMLogic (300) embodiment version, as subject of this invention, containinga four inputs one output NOR3 (307) logic gate, a two inputs one outputRS logic Latch including two NOR gates NOR4 (311) and NOR5 312 whichuses only its Q-bar (inverting) output (similarly to the one shown inFIG. 6 g1), five current buffers BUF1 (313), BUF2 (314), BUF3 (315),BUF4 (316), BUF5 (317), and an inverting buffer INVar (318).

BUF1 (313) input is coupled to SD2 (306) and its output is coupled tothe first input of NOR3 (307). BUF2 (314) output is coupled to Y (305)and its input is coupled to the NOR3 (307) output. BUF3 (315) input iscoupled to SD1 (304) and its output coupled to the fourth input of NOR3(307). BUF4 (316) input is coupled to R (301) and its output coupled toone input of NOR4 (311). The other input of NOR 4 (311) together withthe NOR5 (312) output are coupled to the second input of NOR3 (307). Theother input of NOR5 (312) is coupled to the third input of NOR3 (307)and to the output of BUF5 (317). The input of BUF5 (317) is coupled to S(303). The output of INVar (318) is coupled to ARSP (302) and its inputis coupled to the output of NOR3 (307).

As further embedded herein, the AR-PWM Logic (300) block, provides anoutput signal at Y (305) function of the momentary voltage levelprovided to its inputs electrodes, in accordance to the truth tableshown in FIG. 6 h 3, as long as the voltage amount inputted to the twoprotection inputs SD1 (304) and SD2 (306), remains at the LOW logiclevel. If at least one of this protection inputs is in HIGH logic state,than the Y (305) output is LOW.

The INVar (318) provides, trough ARSP (302) the necessarily synchronizedsignal to the CARin (701) input of the ARC (700) block, which this timeis in opposite phase.

23.4 Design and Implementation

The AR-PWM sub-circuit can be easily designed and implemented in a mixedsignal circuit, by using the classic PWM circuit's output (Y) signal asan analog reset sync pulse, however there is a need of a “low noise”control operation, in order to achieve a high performance Analog ResetPWM sub-circuit. Therefore, an “open collector” (pull down only) bufferof the output's (Y) signal is recommended.

23.5 Conclusions

The AR-PWM is a novel circuit, however its implementation is simple,provides considerable flexibility in design and parts selection and doesnot request expensive extra parts for obtaining a high performancesmixed signal circuit.

The ARS-PWM Hybrid Controller Circuit Embodiments

24.1 General Description

The core of a CPPC PCF Controller Circuit (100) consists in a highperformances Voltage Mode PWM circuit, able to deliver a very short(10-100 nS) driving pulse.

The (any manufacturer) “xx384x” Current Mode Controllers series,provided since a long time ago by over fifty worldwide manufactures, hasalmost all necessarily attributes for being included into a highperformances CPPC PCF CC (100), except the ability to provide a veryshort driving pulses in the Voltage Mode of operations.

Therefore, an ARS-PWM Hybrid Controller Circuit (800) is provided, whichis able to resolve this important inconvenient. For the reminder of thisdescription the ARS-PWM Hybrid Controller Circuit (800) may be referredto as an ARS-PWM HCC (800).

In this chapter of the present invention, a high performances VoltageMode PWM circuit embodiment is achieved by the means of an Open-loopTest Fixture Circuit which comprises all necessarily parts (including avoltage ramp driver for allowing the Voltage Mode of Operations) fortesting an ARS-PWM HCC (800), which includes a xx3842 and a few extraparts.

This ARS-PWM HCC (800) represents an immediately evidence of the AnalogRest Method implementation into a classic, low cost, current mode PWMcontroller external circuit, for obtaining a high performances VoltageMode PWM circuit, as a final step for achieving a high performance CPPCPCF Controller Circuit (100).

The ARS-PWM HCC (800) has an identical pin-out configuration to theclassic xx3842 controller, is able to replace with no modifications ofthe external circuit a xx3842 device, as a current mode PWM controller,however it has the advantage of working also as a High PerformancesVoltage Mode PWM Controller Circuit.

In other words, each of the ARS-PWM (800) Hybrid Controller Circuitembodiment version presented below, contains a xx3842 (830) device whichhas its terminals coupled to the ARS-PWM HCC (800) I/O electrodes in thesame 8 pin-out configuration, respectively Comp to Comp (801), FB to FB(802), Is to Is (803), RC to RC (804), GND to GND (805), Out to Out(806), Vcc to Vcc (807) and Vref to Vref (808) and a few extra low costparts.

In this way, a highly improved current and/or voltage mode PWMcontroller circuit is achieved, without making any alteration to theoriginal controller function and/or its pin-out topography.

Therefore, during the description of the three embodiments presentedbelow, it is assumed that each of the ARS-PWM HCC (800) I/O electrodesis internally connected to its similar name terminal of the xx3842(830).

24.2 The 1^(st) ARS-PWM Hybrid Controller Embodiments

FIG. 24A shows an Open Loop Laboratory Fixture, identical (with respectto the parts attributes) to the one presented above at FIG. 4 of therelated art section, for a comparison test of the ARS-PWM HCC (800), assubject of this invention, and a classic UC3842 device.

Internally, the first version of the ARS-PWM HCC (800) contains anUC3842 (830) device, a resistor Rar (831), a low voltage zener diode Zar(832), a high frequency diode Dar (833) and a low value capacitor Cdar(834).

The UC3842 (830) device is coupled, pin by pin, in the same 8 pinconfiguration as the ARS-PWM HCC (800) I/O electrodes (as has beenexplained above).

One terminal of Rar (831) is coupled to Out (806) and the other terminalis coupled to the cathode of Zar (832) and to the cathode of Dar (833).The anode of Dar (833) is coupled to Is (803) and to one terminal ofCdar (834). The other terminal of Cdar (834) and the anode of Zar (832)are coupled together to GND (805).

Externally to the ARS-PWM HCC (800), there is a test fixture circuit,similarly to the one described in the related art section, comprising afirst error amplifier resistor Real (811) an error amplifier voltagelevel adjuster potentiometer P1 (812), a compensation resistor Rp (813),a second error amplifier resistor Rea2 (814), an oscillator timingresistor Rt (815), an oscillator timing capacitor Ct (816), a voltageramp driver transistor Qvr (817), an Isense (i.e. max duty cycle)adjuster potentiometer P2 (818), a Vref filtrating capacitor Cvref(819), a Vdc filtrating capacitor Cvdc (820), a drive pulse loadresistor Rdrv (821) and a voltage DC source Vdc (822).

Real (811), is coupled between Vref (808) and one terminal of P1 (812).The middle connection of P1 (812) is coupled directly to FB (802) andvia Rcomp (813) to Comp (801). The other terminal of P1 (812) is coupledto GND (60) via Rea2 (814). Rt (815) has one terminal coupled to Vref(808) and the other one coupled simultaneously to the base of Qvr (817),RC (804) and one terminal of Ct (816). The other terminal of Ct (816) iscoupled to GND (60). Qvr (817) has its collector coupled to Vref (808)and its emitter coupled to GND (60) via P2 (818). The middle connectionof P2 (818) is coupled to Is (803). Vref (808) is coupled to GND (60)via Cvref (819), Vcc (807) is coupled to GND (60) via Cvdc (820), Out(806) is coupled to GND (60) via Rdrv (821) and GND (805) is coupleddirectly to GND (60).

Vdc (822) has its positive pole coupled to Vcc (807) and its negativepole to GND (60).

As further embedded herein, the resistor Rar1 (831) together with thediode Dar (833) provide an Analog Reset sync signal to the Is (803)input of the internal current sense comparator of the UC3842 (830). Bymaintaining the Is (803) input near 0v during the time when Out (806) islow, the current sense comparator has time to switch LOW before the nextSET pulse is delivered. The zener diode Zar (832) limits the Analogreset pulse to an amount less than 5v and the capacitor Cdar (834)integrates the short spike (noise) created when the Out (806) drivingpulse gets HIGH, because of the Dar (833) parasite capacitance.

24.3 The 2^(nd) ARS-PWM Hybrid Controller Embodiments

FIG. 24B shows a second ARS-PWM HCC (800) embodiment version. The sameOpen Loop Laboratory Fixture circuit presented in FIG. 24A is used for acomparison test of this new ARS-PWM HCC (800), as subject of thisinvention, and a classic 3842 device.

Internally, the second embodiment version of the ARS-PWM HCC (800)contains an UC3842 (830) device, a first analog reset biasing resistorRar1 (841), a first analog reset transistor Qar1 (843), a second analogreset biasing resistor Rar2 (843) and a second analog reset transistorQar2 (844).

The UC3842 (830) device is coupled, pin by pin, in the same 8 pinconfiguration as the ARS-PWM (800) Hybrid Controller Circuit I/Oelectrodes (as has been explained above).

One terminal of Rar1 (841) is coupled to Out (806) and the otherterminal is coupled to the base of Qar1 (842). Qar1 (842) has is emittercoupled to GND (805) and its collector coupled to the base of Qar2 (844)and one terminal of Rar2 (843). The other terminal of Rar2 (843) iscoupled to Vref (808). Qar2 (844) has its emitter coupled to GND (805)and its collector coupled to Is (803).

Externally to the ARS-PWM HCC (800), the same test fixture circuitillustrated in FIG. 24A is used for comparison test to the classicxx3842 device.

In other words, the ARS-PWM HCC (800) version from FIG. 24B replaces,pin by pin, the ARS-PWM (800) Hybrid Controller Circuit version fromFIG. 24A.

As further embedded herein, the circuit including Rar1 (841), Qar1(842), Rar2 (843) and Qar2 (844) provides an Analog Reset sync signal tothe Is (803) input of the internal current sense comparator of thexx3842 (830).

By maintaining the Is (803) input near 0v during the time when Out (806)is low, the current sense comparator has time to switch LOW before thenext SET pulse is delivered.

24.4 The 3^(rd) ARS-PWM Hybrid Controller Embodiments

FIG. 24C shows a third ARS-PWM HCC (800) embodiment version. The sameOpen Loop Laboratory Fixture circuit presented in FIG. 24A is used for acomparison test of this new ARS-PWM HCC (800), as subject of thisinvention, and a classic 3842 device.

Internally, the third embodiment version of the ARS-PWM (800) HybridController Circuit contains, besides an UC3842 (830) device, a analogresetting capacitor Car (851) and a separation resistor Rars (852).

The UC3842 (830) device is coupled, pin by pin, in the same 8 pinconfiguration as the ARS-PWM (800) Hybrid Controller Circuit I/Oelectrodes (as has been explained above), except the Is pin, which iscoupled to Is (803) via Rars (852).

One terminal of Car (841) is coupled to RC (804) and the other terminalis coupled to Is (803). One terminal of Rars (841) is coupled to theUC3842 (830) Is pin and the other terminal is coupled to the Is (803)input electrode of the ARS-PWM HCC (800).

Externally to the ARS-PWM HCC (800) the same test fixture circuitillustrated in FIG. 24A is used for comparison test to the classicUC3842 device.

In other words, the ARS-PWM HCC (800) version from FIG. 24C replaces,pin by pin, the ARS-PWM HCC (800) version from FIG. 24A.

As further embedded herein, the capacitor Car (851) provides an AnalogReset sync signal to the Is (803) input of the internal current sensecomparator of the xx3842 (830). By storing a DC voltage during the timewhen RC (804) increases it voltage amount and pushing the Is (803) inputnear 0v during the time when the RC (804) voltage amount drops to itsinitial value, the current sense comparator has time to switch LOWbefore the next SET pulse is delivered.

The separation resistor Rars (852) is necessarily only if P2 (818)appears as a too small impedance (i.e. less than 5k) for the analogreset capacitor's Car (851) periodically charge and discharge status.

24.5 Design and Implementation

The ARS-PWM HCC sub-circuit can be easily designed and implemented, byusing a classic 384x circuit and a few low cost parts attached.

Bench prototype's data proves that, by using one of the above describedhybrid circuit, a 10-50 times shorter output driving pulse can beachieved, despite the manufacturer and/or quality (i.e. cost) of theclassic 384x controller circuit choused for test.

24.6 Conclusions

The ARS-PWM HCC is a novel sub-circuit included in a PFC circuit,however its implementation is simple, provides considerable flexibilityin design and parts selection and does not request expensive extra partsfor obtaining a high performances voltage mode PWM circuit.

The CPPC-ARS PFC Circuit Apparatus Embodiment

25.1 General Description

In accordance with the present invention, a Low Cost High PerformancesPower Factor Correction System—LCHPPFCS (1) Apparatus Embodiment isprovided, comprising a Power Factor Correction Large Signal CircuitPFC-LSC (2) and a Power Factor Correction Small Signal Circuit PFC-SSC(3).

The Apparatus PFC-LSC (2) sub-circuit is pretty similar to the oneillustrated in FIG. 14 and the implementation of the CPPC Method ofcontrolling the Power Factor in a Large Signal Circuit has been fullydescribed already in Chapter 14 of the present patent application.

The Apparatus PFC-SSC (3) sub-circuit is pretty similar to the oneillustrated in FIG. 15 and the implementation of the CPPC Method in thisPFC Small Signal Circuit, including a NEWCTRL (100) and a CRC (110), hasbeen also fully described already in Chapter 15 of the present patentapplication.

The Apparatus' NEWCTRL (100) Embodiment has been designed in accordanceto the block schematic diagram illustrated in FIG. 15 however, for the“Low Cost” target purposes, it has been implemented in a hybrid circuitconfiguration, including an ARS-PWM HCC (800) sub-circuit and some extradiscreet devices (attached externally to the ARS-PWM HCC (800), butstill considered as internal parts and/or functional blocks in respectto the NEWCTRL (100) circuit), for the implementation of the rest of theNEWCTRL (100) functional blocks.

In other words, in order to achieve the “13 functional blocksarchitecture” of the NEWCTRL (100) circuit illustrated in FIG. 15, ahybrid circuit version embodiment is provided, in which nine of thethirteen functional blocks are included in the UC3842 (830) device($0.27/unit) and the other four blocks are represented by a few discreetparts (about $0.10 total extra cost).

Therefore, since the total cost of this PFC controller circuit is lessthan $0.40 in this hybrid configuration, obviously by re-designing andbuilding (as an eventually next step) in just “one piece of silicon”(i.e. full custom design) the entire NEWCTRL (100) circuit, the totalcost can be even more reduced, targeting a large volume price comparableto the existing UC384x current mode PWM controllers family.

25.2 The CPPC PFC-LSC

Reference will now be made in detail to the present embodiment of theinvention, illustrated in the accompanying drawing.

In accordance with the present invention, in FIG. 25 a PFC-LSC (2)Apparatus Embodiment is provided as an important LCHPPFCS (1)sub-circuit.

The PFC-LSC (2) includes, in this embodiment's version, an alternativecurrent Voltage generator Vac (10), a Low (frequency) Pass Filter blockLPF (20), a Bridge Rectifier block BR (30), a Complex Load block CL (40)and a generic Boost CPPC PFC-IC (50).

The Vac (10) is a low frequency (50-60 Hz) high voltage (90-240Vrms)sine wave voltage generators which provides a full rectified AC voltageto CPPC PFC-LSC (50), trough the LPF (20), comprising two filtratingcapacitor Cf1 (21) and Cf2 (23) flanking a symmetrical double coil Lf1(22) and also trough the BR (30), comprising four rectifier diodes DR1(31), DR2 (32), DR3 (33) and DR4 (34).

The CL (40), comprising a resistive load RI (41) across to a bulk(100-470 uF) capacitor Cb (42), is supplied by (and/or trough) the BoostCPPC PFC-IC (50) block.

The Boost CPPC PFC-IC (50), as embodied herein, is a complex functionalblock having six I/O electrodes, respectively two large signal inputelectrodes Vin+ (51), Vin− (52), two large signal output powerelectrodes Vo− (53), Vo+ (54) and two small signal electrodes such asDRVin (58) and VRs (59).

Internally, the generic boost CPPC PFC-IC (50) block, as embodiedherein, contains a two terminals oscillating coil L1 (61), a high powerfast (30-500 kHz) rectifier diode D1 (62), a high power high frequency(30-500 kHz) MOSFET transistor M1 (63), a sense resistor Rs (65) and acapacitor CVin (64).

The coil L1 (61) has one terminal coupled to Vin+ (51) and the other onecoupled to the anode of D1 (62). The cathode of D1 (62) is coupled toVo+ (54). M1 (63) has its drain electrode coupled to the anode of D1(62), its source electrode to Vin− (52) via Rs (65) and its gateelectrode coupled to DRVin (58). CVin (64) is coupled across Vin+ (51)and Vin− (52). Vin− (52) is coupled to Vo− (53) and is also coupled tothe system's ground GND (60).

The BR (30) has its AC input coupled to the LPF (20) output, itspositive output coupled to Vin+ (51) and its negative output to Vin−(52).

The CL (40) is coupled across the two output electrodes, Vo+ (54) andVo− (53).

25.3 The CPPC PFC-SSC

A CPPC PFC SSC (3), as a complementary sub-circuit for the CPPC PFC LSC(2), in respect to the entire LCHPPFCS (1) is also provided in FIG. 25,including a constant pulse proportional current power factor correctioncontroller circuit CPPC PCF CC (100) and a controller's related circuit,CRC (110). The CPPC PCF CC (100) may be referred to as NEWCTRL (100).

25.4 The Controller Circuit

The figures suggest that the NEWCTRL (100) improves the power factor inthis circuit and the positions of the various terminals denote thefunction of each of them. In other words, in a NEWCTRL (100) schematicdiagram, the internal architecture and the positions of the terminalswill illustrate, alone, the particular function of each terminal.

As farther embedded herein, the NEWCTRL (100), subject of thisinvention, is a Complex Mixed Signal System connected to the rest of theLCHPPFCS (1) via eight I/O electrodes: a feedback electrode FB (101) acompensation electrode (102), a non-linearity correction electrode NLC(103), a soft start electrode SS (104), a ground electrode GND (105), acurrent limiter electrode 111 m (106), a gate driving electrode DRV(107) and a supply electrode VCC (108). A zero voltage internalconnection 0v (109) serving as internal ground is connected to the GND(105) electrode.

Internally the NEWCTRL (100) contains oscillating charging resistor Rch(441), an oscillating and voltage ramp provider capacitor (442), avoltage ramp driver NPN transistor VRD2 (561), a first voltage driveresistor Rvrd2 (562), a second voltage ramp resistor Rvr3 (563), a softstart PNP transistor Qss (453), a soft start resistor Rss (454), a softstart diode Dss (455), a start enforcer resistor Rse (753), a startenforcer diode Rse (754) and an AR-PWM (800), sub-circuit.

The AR-PWM (800) has its 1^(st) terminal “Comp” coupled to Comp (102),its 2^(nd) terminal coupled to FB (101), its 3^(rd) terminal “Is”coupled to HVC via Rvr2 (562) and to Him (106) via Rvr3 (563), its4^(th) terminal coupled to Vref (8^(th) terminal) via Rch (441) and to0v (109) via Cvr (442), its 5^(th) terminal GND coupled to 0v (109) andto GND (60), its 6^(th) terminal Output coupled to DRV (107) its 7^(th)terminal Vcc coupled to Vcc (108) and its 8^(th) terminal Vref coupled(besides Rch (441) which has been mentioned already), to the cathode ofDse (754), collector of VRD2 (561), one terminal of Rss (454) andcathode of Dss (455). The anode of Dse (754) is coupled to FB (101) viaRse (753). The NPN transistor VRD2 (561) has its base coupled to RC (the4^(th) terminal of ARS-PWM (800) and its emitter coupled to HVC (103).The other terminal of the Rse (454) is coupled to the base of Qss (453),to the anode of Dss (455) and to SS (104). The Qss (453) emitter iscoupled to Comp (102) and its collector is coupled to 0v (109).

In respect to the block schematic diagram of the NEWCTRL (100) internalcircuit presented in FIG. 15 and the ARS PWM HCC (800) Embodimentspresented in FIG. 19, the AR-PWM (800) sub-circuit comprises thefollowing functional blocks: ISP (150), DR (200), Vref (250), PWM-Logic(345), OSC (445), VEA (600), VL (650) and C (745).

By the means of one of the AR sub-circuits illustrated in FIG. 24 andfully described above (Chapter 24), the classic UC3842 (830) pulse widthmodulation comparator C (745) has been forced to perform as an ARC(700), fact which guarantees a very short ON driving pulse, when isneeded (by resetting periodically its “Is” input).

The SS (450) block is represented by a circuit (presented in FIG. 17 anddescribed above) comprising Qss (453) Rss (454) and Dss (455), the SE(750) block is represented by a circuit (presented in FIG. 17 anddescribed above) comprising Rse (753) and Dse (754) and the VRD (595)block is represented by a classic voltage ramp driving circuitcomprising VRD2 (551), Rvr2 (552) and Rvr3 (553).

The current limiter comparator block CL (350) is overlapping with theARC (700) block, and the non-linearity correction block NLC (500) isoverlapping with the VRD (595) block.

25.5 The Controller's Related Circuit

The Controller Related Circuit (110) includes typically just the smallsignal devices direct connected to the NEWCTRL (100), most of them fullydescribed in Chapter 15 (FIG. 15) above, however in some situations itmay include also the Controller Self-Supply Circuit CSSC (90), fullydescribed in Chapter 14 (FIG. 14), for the applications where no other16-20v DC supply voltage is available.

In this embodiment it is assumed that there is an available 16-20V DCvoltage source VDC (121) for supplying the NEWCTRL (100) circuit.

As FIG. 25 shows, externally to the NEWCTRL (100), the controllerrelated circuit CRC (110) includes a first feedback resistor Rfb1 (111),a second feedback resistor Rfb2 (112), a compensation capacitor Cc(113), a first non linearity correction resistor Rnlc1 (114), a softstart capacitor Css (116), a supply filtrating capacitor Vdc (117), adriving resistor Rdr (118), a current sense limiting resistor Ris (119),a current sense signal filtrating capacitor Cis (120) and a directcurrent voltage source VDC (121).

The CRC (110) connects the NEWCTRL (100) with the rest of the circuit asfollowing:

The FB (101) electrode is coupled to Vo+ (54) via Rfb1 (111), to GND(60) via Rfb2 (112) and to Comp (102), via Cc (113). The HVC (103)electrode is coupled to Vin+ (51) via Rnlc1 (114). The SS (104)electrode is coupled to GND (60) via Css (116). The GND (105) electrodeis coupled to GND (60). The Ilim (106) electrode is coupled to Vrs (59)via Ris (119) and to GND (60) via Cis (120). The DRV (107) electrode iscoupled to DRVin (58) via Rdr (118). The Vcc (108) electrode is coupleddirectly to the positive pole of a 16-20V supply source VDC (121) and toGND (60) via Cdc (117). The VDC (121) has its negative pole coupled toGND (60).

Eventually, Vcc (108) can be coupled to VDC+ (92) provided by CSC (90),as it has been illustrated in FIG. 14 and described above.

25.6 The LCHPPFCS Apparatus

As has been already described in Chapter 14, the CPPC PCF LSC (2) isable to improve near unity the power factor in a LCHPPFCS (1), as longas a proper “Constant Pulse” is provided by the CPPC SSC (3).

As further embodied herein, when a voltage is applied to the Boost CPPCPFC-IC (50) having the positive polarity at Vin+ (51) and the negativepolarity at Vin− (52) and M1 (63) is OFF, a DC voltage is created acrossthe complex load CL (40), respectively across Vo+ (54) and Vo− (53), inan amount slightly lower than the peak input voltage (classic BridgeRectifier-Bulk Capacitor AC/DC converter). As has been explained in theRelated Art section, initially the Vac (10) current shape in thiscircuit is similarly to the one shown in FIG. 26, B and therefore thesystem Power Factor parameter is about 0.65 or less.

When NEWCTRL (100) starts commuting M1 (63) ON/OFF with a high frequency(30-500 kHZ), the DC voltage level across Vo+ (54)-Vo− (53) willincrease to a higher amount than the input peak voltage, because of theelectrical energy stored periodically by L1 (61) during the ON time ofM1 (63) and delivered periodically, via D1 (62) to CL (40), during theOFF time of M1 63). The value of CVin (64) is too small to alter thesystem's power factor, but large enough (100-220 nF) for protecting BR(30) for reverse high frequency oscillations.

As soon Cb (42) is charged up to a higher value than the input peakvoltage, there is no more direct current between Vac (10) and CL (40),because BR (30) and D1 (62) are reverse polarized. Starting from thismoment, the circuit's input current shape depends of the L1 (61)circuit's current only.

In other words, the Vac (10) does not “feel” anymore in its circuit thebulk capacitor Cb (42), which is the only one device able to reducesubstantially the entire circuit's power factor.

If the charging/discharging time is constant in frequency and duty/cycleand the ON time is short (and/or OFF time is long) enough for keepingthe coil L1 (61) within its linear range (in other words to prevent thecoil's core saturation), then the L1 (61) circuit's current is directproportional to the amount of its supply voltage.

Since the voltage inputted at Vin+ (51) is a full rectified sine wave,the L1 (61) circuit's momentary current's value must follow a rectifiedsine wave's shape.

Therefore, as soon the output voltage is higher (preferable 1.5-2 times)than the input peak voltage, the Vac (10) current shape changesimmediately to a form similarly to the one illustrated in FIG. 26, E(almost a sine wave) without a need for a sophisticated classic“Multiplier” to be involved in the controller circuit.

If the NEWCTRL (100) frequency and duty/cycle are properly set (see FIG.27A 1-4), in respect to the L1 (61) inductance, max Vin+ and the maxload current, then the M1 drain voltage shape could be any of the onesillustrated in FIG. 27B 1-4 and the M1 drain current shape could be anyof the ones illustrated in FIG. 27C 1-4 (discontinuous mode ofoperation).

However, if the NEWCTRL (100) frequency and duty/cycle are not properlyset (i.e. OFF time to short and/or ON time too long—see FIG. 27A 5), inrespect to the L1 (61) inductance, max Vin and the max load current,then the M1 drain's voltage shape could be the one illustrated in FIG.27B 5 and the M1 drain current shape could be the one illustrated inFIG. 27C 5 (continuous mode of operation).

For a high Power Factor parameter (i.e. PF>0.99) the mode of operationsmust remain unchanged during, at least one Vac (10) semi-cycle.

25.7 Design and Implementation

The implementation of the Constant Pulse Proportional Current PowerFactor Correction method in an AC/DC converter is much simple than anyother related art methods (especially the ones involving a Multiplier),providing considerable flexibility in design and parts selection.

A completed LCHPPFCS (1) apparatus design project is illustrated in FIG.36 to FIG. 39, including the prototype schematic diagram (similarly tothe one illustrated in FIG. 25), the parts list and the bench test data,collected with a Voltech PM 100.

The Power Analyzer Voltech PM 100 (recognized worldwide as a “1^(st)Class” test tool) is able to provide, in just one Test Data Sheetpicture, all significant performances of a AC/DC converter, such as the“RMS Results”, the “Fundamental Results”, the “Inverse DFT Waveform”(the input current vs. voltage graph) and the Harmonic Spectrum barsgraph.

The table illustrated below shows the most significant data collectedduring the present invention's Apparatus (bench prototype) test. Fig.Vin lin Pin Pin Vo RI Po Eff. PF A.THD # (V) (A) (W) (VA) (V) (K) (W)(%) (—) (%) Comments 37A 93.6 2.35 164.6 219.8 115.5 0.083 159.8 97.10.749 76.0 NO PFC 37B 90.0 1.84 164.4 165.9 389.7 1.0 151.9 92.4 0.99110.4 OPEN LOOP 37C 90.2 1.86 168.0 168.2 393.4 1.0 154.8 92.1 0.999 2.83NO NLC 37D 90.3 1.88 169.4 169.6 395.1 1.0 156.1 92.2 0.999 3.90 FULLSYS 38A 125.6 1.82 166.5 229.0 159.4 0.157 162.4 97.5 0.727 84.1 NO PFC38B 120.9 1.37 164.3 165.3 393.5 1.0 134.8 94.2 0.994 8.20 OPEN LOOP 38C120.7 1.37 165.5 165.7 394.5 1.0 155.6 94.0 0.999 1.81 NO NLC 38D 120.71.38 166.9 167.0 395.7 1.0 156.6 93.9 0.999 0.88 FULL SYS 39A 240.7 1.05164.4 252.2 317.4 0.625 161.2 98.1 0.652 106.9 NO PFC 39B 240.8 0.71161.7 171.5 397.8 1.0 158.2 97.9 0.942 32.5 OPEN LOOP 39C 240.5 0.71162.8 170.5 397.5 1.0 158.0 97.0 0.955 28.4 NO NLC 39D 240.7 0.68 163.8164.2 397.7 1.0 158.2 96.6 0.998 4.00 FULL SYS

The above table presents (comparatively) the present invention's 160wPFC Apparatus prototype's performances, over a wide range of the inputvoltage such as 90Vrms used in Japan, 120Vrms used in USA and 240Vrmsused in Europe, in respect to four different circuit configurations: “NOPFC”, “OPEN LOOP”, “NO NLC” and “FULL SYS”.

The “NO PFC” data lines collected from the Test Data Sheets illustratedin FIG. 37A, FIG. 38A and FIG. 39A represents the start point referencefor all the other circuit configurations.

Before the NEWCTRL circuit has been supplied with DC voltage, there areno HF oscillations, so the entire circuit acts as a classic AC/DCconverter apparatus, which confirms all the above statements referred toa classic AC/DC converter, such as:

The input current's RMS values (Amps) is much higher than were supposedto be (see the “lin” amount after the PFC has been applied), fact thatconsiderable (about 40%) increase the VA input (Apparent) Power'samount.

In respect to the other circuit's configurations, the PF parameterreaches very low values (0.65-0.75), the A.THD parameter reaches veryhigh values (76-107%) and the efficiency reaches its maximum value(97-98%).

The current (vs. voltage) graph shape (Inverse DFT Waveforms section)looks more like a triangle than a sine wave.

The Harmonic Spectrum Graph bars graph section of each of the abovementioned figures' Test Data Sheet (37A, 38A, 39A), shows a significant“noise level” especially in the 3^(rd) and the 5^(th) harmonicsfrequency range.

The “OPEN LOOP” data lines collected from the Test Data Sheetsillustrated in FIG. 37B, FIG. 38B and FIG. 39B reflect the NEWCTRLcircuit's performances in the first step of the “Constant Pulse” methodimplementation. An appropriated constant DC voltage amount has beenapplied to the NEWCTRL's “FB” input electrode and the “NLC” inputelectrode as well as the “Ilim” input electrode, have been disconnected(in air) from the external circuit, in order to see the performances ofthe CPPC method's in its most simple way of implementation.

This apparatus circuit configuration confirms all the above statementsreferred to the implementation of the CPPC method in a boost convertercircuit, such as:

The input current's RMS values (Amps) is much lower than in “NO PFC”situation, fact that keeps the VA input (Apparent) Power's amount closedto the W input (Real) Power amount.

In respect to the “NO PFC” configurations, the PF parameter reaches muchhigher values (0.942-0.994), the A.THD parameter reaches much lowervalues (8-32%) and the efficiency reaches better values at higher inputvoltage (92.4-97.9%).

The current (vs. voltage) graph shape (Inverse DFT Waveforms section)looks closed to a sine wave at low input voltage (90-120Vrms), howeversome (non linearity) distortions appear at high input voltage (240Vrms)only.

The Harmonic Spectrum Graph bars graph section of each of the abovementioned figures' Test Data Sheet shows low “noise level” when theinput voltage is low (FIG. 37B and FIG. 38B), however the noiseincrease, especially in the 5^(th) harmonic frequency range, when a highinput voltage (240Vrms) is applied (FIG. 39B).

The “NO NLC” data lines collected from the Test Data Sheets illustratedin FIG. 37C, FIG. 38C and FIG. 39C reflect the NEWCTRL circuit'sperformances in the second step of the “Constant Pulse” method'simplementation. The NEWCTRL's “FB” input electrode and the “Ilim” inputelectrode have been connected to the external circuit, however the NLCinput electrode remains disconnected (in air), in order to show theresults of the CPPC method's in closed feedback circuit, before any nonlinearity correction is applied.

Similarly to the previous version, this apparatus circuit configurationconfirms all the above statements referred to the implementation of theCPPC method in a boost converter circuit, delivering even betterresults, such as:

In respect to the “OPEN LOOP” configurations, the PF parameter reacheshigher values (0.955-0.999), the A.THD parameter reaches lower values(1.81-28.4%).

The current (vs. voltage) graph shape (Inverse DFT Waveforms section) isalmost a sine wave at low input voltage (90-120Vrms), however somedistortions still remains at high input voltage (240Vrms) only.

The “FULL SYS” data lines collected from the Test Data Sheetsillustrated in FIG. 37D, FIG. 38D and FIG. 39D reflect the NEWCTRLcircuit's performances in the last step of the “Constant Pulse” methodimplementation. All NEWCTRL's electrodes are connected to the externalcircuit, in order to see the final performances of the full CPPC PFCSystem and more specific the improvements achieved by introducing theNLC circuit.

Similarly to the previous version, this apparatus circuit configurationconfirms all the above statements referred to the implementation of theCPPC method in a boost converter circuit, delivering even betterresults, such as:

In respect to the “NO NLC” configurations, the PF parameter reachesalmost the perfection (0.998-0.999) and also the A.THD parameter reachesmuch lower values (0.88-4.00%).

The current and voltage graphs shapes (Inverse DFT Waveforms section)look almost identical at low input voltage (90-120Vrms), however somevery small (non linearity) distortions still appear at high inputvoltage (240Vrms) only. Since the cheapest NLC circuit version has beenchoused, respectively a $0.001 resistor (Rnlc1=2.7M/0.25w), theperformances are anyway beyond the expectations.

The Harmonic Spectrum Graph bars graph section of each of the abovementioned figures' Test Data Sheet show low (i.e. acceptable) “noiselevel” for all harmonics.

25.8 Conclusions

This significant cost saving for a High Performances PFC ControllerCircuit, down to almost a Current Mode PWM Controller Circuit'sprice/unit, is made possible only by the means of the novel CPPC and ARScontrolling methods' implementation.

These two novel PFC controlling methods' implementation, allow for highperformances by using a low cost PCF Large Signal Circuit (low sizeoscillating inductor, i.e. 100 uH) as well as for a low cost PCF SmallSignal Circuit (low cost controller circuit and low parts count,controller related circuit).

The Comparison Chart illustrating comparatively the NEWCLRL (100)features (performances/cost) versus two of the most appreciated PFCControllers Circuits existing solutions of the worldwide Related Art,presented in one of the introductory section of this patent application(Chapter 6: Brief Summary pg. 14) together with the apparatus bench testdata results, may be considered as references and/or evidences for allthe above statements.

Additionally, the NEWCTR (100) does not require a sophisticated and/orexpensive related circuit, so its implementation into a complete PFCSystem (including the LSC devices) is basically as simple as the onerequested by any classic UC384x series PWM controller.

1. A power factor correction system for improving near unity theelectrical energy transfer's power factor parameter in a low frequencyAC power source to a complex load circuit, the system comprising: an ACpower source for providing a low frequency supply signal; a fullrectifier circuit having a negative output and a positive outputoperatively connected to the AC power source for converting the AC powersource supply signal into a low frequency fully rectified supply signal;a high frequency controllable C/DC boost converter circuit operativelycoupled to the full rectifier circuit for converting the low frequencyfully rectified supply signal first into a high frequency supply signaland finally into a DC voltage output higher in amount than the lowfrequency fully rectified supply signal's peak voltage amount,comprising: a capacitive circuit coupled across the output of therectifier circuit, properly sized for having high impedance in respectto the AC power source low frequency supply signal and low impedancewith respect to the converter high frequency supply signal; anoscillating inductor coupled at one end to the positive output of therectifier circuit, the inductor having a charging time and a dischargingtime and the inductor being properly sized so that the momentary currentamount across the inductor increases linearly and direct proportionalwith its supply voltage and/or its charging time amount, for deliveringa high frequency pulse signal during its discharging time; acontrollable power switch circuit coupled at one end to the other end ofthe oscillating inductor the switch is coupled at the other end to thenegative output of the bridge circuit for periodically charging theoscillating inductor in accordance with a high frequency driving pulsesignal; and a high frequency rectifier diode having an anode and acathode the anode is coupled to the second end of the oscillatinginductor and one end of the power switch and the cathode is connected tothe DC/DC converter circuit output; a complex load including at leastone capacitive circuit able to stone the converter's DC voltage output,the complex load having a positive end and a negative end, the positiveend of the complex load being coupled to the DC/DC converter circuit'soutput and the negative end of the complex load is coupled to thenegative output of the full rectifier circuit; and a high frequencycontroller circuit capable to provide the controllable switch with aproper driving pulse signal including trains of pulses constant infrequency and duty cycle during a time equal to or longer than onesemi-cycle period of the AC power source supply signal so that thecurrent amount absorbed by the DC/DC converter from the AC power sourceis contingent and linearly proportional to the AC power source supplysignal voltage's amount only, as long the DC voltage stored in thecomplex load's capacitive circuit is higher in amount than the lowfrequency fully rectified supply signal's peak voltage amount.
 2. Apower factor correction system for improving near unity the electricalenergy transfer's power factor parameter in a low frequency AC powersource to a complex load circuit, the system comprising: an AC powersource for providing a low frequency supply signal; a low frequency passfilter circuit for protecting the power source against reverse highfrequency signal noise; a full rectifier circuit having a negativeoutput and a positive output operatively connected to the AC powersource for converting the AC power source supply signal into a lowfrequency fully rectified supply signal; a high frequency controllableDC/DC buck-boost converter circuit operatively coupled to the fullrectifier circuit for converting the low frequency fully rectifiedsupply signal first into a high frequency supply signal and finally intoa DC voltage output, comprising: a capacitive circuit coupled across theoutput of the rectifier circuit, properly sized for having highimpedance in respect to the AC power source low frequency supply signaland low impedance in respect to the converter high frequency signal; anoscillating inductor coupled at one end to the positive output of therectifier circuit, the inductor having a charging time and a dischargingtime and the inductor being properly sized so that the momentary currentamount across the inductor increases linearly and in direct proportionwith its supply voltage and/or its charging time amount, for deliveringa high frequency pulse signal during its discharging time; acontrollable power switch circuit coupled at one end to the second endof the oscillating inductor the switch is coupled at the other end tothe negative output of the bridge rectifier circuit for being able toperiodically charge the oscillating inductor in accordance to a highfrequency driving pulse signal; and a high frequency rectifier diodehaving an anode and a cathode the anode is coupled to the second end ofthe oscillating inductor and one end of the power switch and the cathodeis connected to the AD/DC converter circuit output; a complex loadincluding at least one capacitive circuit able to store the converter'sDC voltage output, the complex load having a positive end and a negativeend, the positive end of the complex load being coupled to the AD/DCconverter circuit output and the negative end of the complex load iscoupled to the positive output of the full rectifier circuit; and a highfrequency controller circuit capable to provide the controllable switchwith a proper driving pulse signal including trains of pulses constantin frequency and duty cycle during a time equal or longer than onesemi-cycle period of the AC power source supply signal so that thecurrent amount absorbed by the AC/DC converter from the AC power sourceis contingent and linearly proportional to the AC power source supplysignal voltage's amount only.
 3. A power factor correction system forimproving near unity the electrical energy transfer's power factorparameter in a low frequency AC power source to a complex load circuit,the system comprising: an AC power source for providing a low frequencysupply signal; a full rectifier circuit having a negative output and apositive output operatively connected to the AC power source forconverting the AC power source supply signal into a low frequency fullyrectified supply signal; a complex load comprising at least one storagecapacitive circuit having a positive end and a negative end, thenegative end of the complex load being coupled to the negative output ofthe bridge rectifier; a high frequency controllable DC/DC highefficiency snubber boost converter circuit operatively coupled to thefull rectifier circuit for converting the low frequency fully rectifiedsupply signal first into a high frequency supply signal and finally intoa DC voltage output, comprising: a first capacitive circuit coupledacross the output of the rectifier bridge, properly sized for havinghigh impedance in respect to the AC power source low frequency supplysignal and low impedance in respect to the boost converter highfrequency signal; a first high frequency rectifier diode having an anodeand a cathode and the cathode of the high frequency rectifier diode iscoupled to the positive end of the complex load; a second high frequencyrectifier diode having an anode and a cathode and the cathode of thehigh frequency rectifier diode is coupled to the positive end of thecomplex load; a third high frequency rectifier diode having an anode anda cathode and the anode of the high frequency rectifier diode is coupledto the positive output of the bridge rectifier; a first oscillatinginductor coupled at one end to the positive output of the bridgerectifier and at the other end to the anode of the first high frequencyrectifier diode, the inductor having a charging time and a dischargingtime and the inductor being properly sized so that the momentary currentamount across the inductor increases linearly and direct proportionalwith its supply voltage and/or its charging time amount, for deliveringto the complex load a high frequency pulse large signal during itsdischarging time; a second oscillating inductor coupled at one end tothe cathode of the third high frequency rectifier diode and at the otherend to the anode of the second high frequency rectifier diode, theinductor having a charging time and a discharging time and the inductorbeing properly sized so that the momentary current amount across theinductor increases linearly and direct proportional with its supplyvoltage and/or its charging time amount, for delivering to the complexload a high frequency pulse large signal during its discharging time; acontrollable power switch circuit having alternatively a ON and a OFFstate coupled at one end to the first oscillating inductor and the anodeof the first high frequency rectifier diode and the switch is coupled atthe other end to the negative pole of the bridge rectifier for beingable to periodically charge during its ON state the oscillatinginductors in accordance to a high frequency driving pulse signal; asecond capacitive circuit coupled at one end to the fist inductor, theswitch and the anode of the first high frequency rectifier diode andcoupled at the other and to the second inductor and the second highfrequency rectifier diode, properly sized for increasing the efficiencyof the converter by not allowing a too fast increased of the switch'svoltage during its OFF period and the second capacitive circuit beingalso properly sized to do not negatively affect the high efficiencysnubber converter circuit's linearity in respect to the average currentabsorbed from the AC generator; and a high frequency controller circuitcapable to provide the controllable switch with a proper driving pulsesignal consisting of trains of pulses constant in frequency and dutycycle during a time equal or longer than one semi-cycle period of the ACpower source supply waves so that the current amount absorbed by thehigh efficiency snubber boost converter from the AC power source iscontingent and linearly proportional to the AC power source supplysignal voltage's amount, as long as the amount of the voltage across thecomplex load is maintained higher than the bridge rectifier peak voltageamount.
 4. A power factor correction system for improving near unity theelectrical energy transfer's power factor parameter in a low frequencyAC power source to a complex load circuit, comprising: a full rectifiercircuit having a negative output and a positive output and common outputoperatively connected to the AC power source for converting the AC powersource signal into a low frequency voltage doubler supply signal; athree terminals complex load having a positive end, a negative end and acommon end, the common end being coupled to the common output of thefull rectifier circuit that is also the common connection of the powerfactor correction system comprising: a first storage capacitive circuitcoupled across the positive end and the common end of the threeterminals complex load; a second storage capacitive circuit coupledacross the negative end and the common end of the three terminalscomplex load; and a resistive circuit coupled across the positive endand the negative end of the three terminals complex load; a controllablehigh frequency voltage doubler DC/DC boost converter circuit operativelycoupled to the bridge rectifier and the complex load for converting thelow frequency fully rectified supply signal into a DC voltage across thecomplex load, higher in amount than the bridge rectifier peak voltageamount for eliminating any direct current between the bridge rectifierand the complex load including: a first capacitive circuit coupledacross the positive output and the common output of the bridgerectifier, properly sized for having high impedance in respect to the ACpower source low frequency supply signal and low impedance in respect tothe boost converter high frequency signal; a second capacitive circuitcoupled across the negative output and the common output of the bridgerectifier, also properly sized for having high impedance in respect tothe AC power source low frequency supply signal and low impedance inrespect to the boost converter high frequency signal; a first highfrequency rectifier diode having an anode and a cathode and the cathodeof the first high frequency rectifier diode is coupled to the positiveend of the complex load; a second high frequency rectifier diode havingan anode and a cathode and the anode of the second high frequencyrectifier diode is coupled to the negative end of the complex load; afirst oscillating inductor coupled at one end to the positive output ofthe bridge rectifier and at the other end to the anode of the first highfrequency rectifier diode, the first inductor having a charging time anda discharging time and the first inductor being properly sized so thatthe momentary current amount across the inductor increases linearly anddirect proportional with its supply voltage and/or its charging timeamount, for delivering to the three terminals complex load a highfrequency pulse large signal during its discharging time; a secondoscillating inductor coupled at one end to the negative output of thebridge rectifier and at the other end to the cathode of the second highfrequency rectifier diode, the second inductor having a charging timeand a discharging time and the second inductor being properly sized sothat the momentary current amount across the second inductor increaseslinearly and direct proportional with its supply voltage and/or itscharging time amount, for delivering to the three terminals complex loada high frequency pulse large signal during its discharging time; a firstcontrollable power switch circuit coupled at one end to the firstoscillating inductor and the anode of the first high frequency rectifierdiode and the first controllable switch is coupled at the other end tothe common output of the bridge rectifier and also coupled to the commonend of the three terminals load for being able to periodically chargethe first oscillating inductor in accordance to a high frequency drivingpulse signal; a second controllable power switch circuit coupled at oneend to the second oscillating inductor and the cathode of the secondhigh frequency rectifier diode and the second controllable switch iscoupled at the other end to the common output of the bridge rectifierand also coupled to the common end of the three terminals load for beingable to periodically charge the second oscillating inductor inaccordance to a high frequency driving pulse signal; and a highfrequency driving transformer comprising: a primary coil able todirectly receive and transfer simultaneously via magnetic field a pulsewidth modulation driving pulse signal to the first and secondcontrollable switches; a first secondary coil operatively connected tothe first controllable switch; and a second secondary coil operativelyconnected to the second controllable switch; and a high frequencycontroller circuit operatively connected to the primarily coil of thehigh frequency driving transformer capable to provide the controllableswitch with a proper driving pulse signal consisting of trains of pulsesconstant in frequency and duty cycle during a time equal or longer thanone semi-cycle period of the AC power source supply waves so that thecurrent amount absorbed by each of the voltage doubler boost convertercircuits from the AC power source is contingent and linearlyproportional to the AC power source supply signal voltage's amount only,as long as the amount of the voltage across the complex load ismaintained higher than the bridge rectifier peak voltage amount.
 5. Apower factor correction system for improving near unity the electricalenergy transfer's power factor parameter in a low frequency AC powersource to a complex load circuit, the system comprising: an AC powersource for providing a low frequency supply signal; a full rectifiercircuit having a negative output and a positive output operativelyconnected to the AC power source for converting the AC power sourcesupply signal into a low frequency fully rectified supply signal; a highfrequency controllable DC/DC converter circuit operatively coupled tothe full rectifier circuit for converting the low frequency fullyrectified supply signal first into a high frequency supply signal andnext into a DC voltage output, comprising: a capacitive circuit coupledacross the output of the rectifier bridge, properly sized for havinghigh impedance in respect to the AC power source low frequency supplysignal and low impedance in respect to the converter high frequencysignal; an oscillating inductor coupled at one end to the positiveoutput of the bridge rectifier the inductor having a charging time and adischarging time and the inductor being properly sized so that themomentary current amount across the inductor increases linearly anddirect proportional with its supply voltage and/or its charging timeamount, for delivering a high frequency pulse signal during itsdischarging time; a controllable power switch circuit coupled at one endto the second end of the oscillating inductor the switch is coupled atthe other end to the negative output of the bridge rectifier for beingable to periodically charge the oscillating inductor in accordance to ahigh frequency driving pulse signal; and a high frequency rectifierdiode having an anode and a cathode the anode is coupled to the secondend of the inductor and one end of the power switch and the cathode isconnected to the DC/DC converter circuit output; a complex loadincluding at least one capacitive circuit able to storage theconverter's DC voltage output, the complex load having a positive endand a negative end, the positive end of the complex load being coupledto the DC/DC converter circuit output and the negative end of thecomplex load is coupled to the negative output of the full rectifiercircuit when the DC/DC converter has a boost configuration or thenegative end of the complex load is coupled to the positive output ofthe full rectifier circuit when the DC/DC converter has a buck-boostconfiguration; and a high frequency controller circuit capable toprovide the controllable switch with a proper driving pulse signalconsisting of trains of pulses constant in frequency and duty cycleduring a time equal or longer than one semi-cycle period of the AC powersource supply signal so that the current amount absorbed by the DC/DCconverter from the AC power source is contingent and linearlyproportional to the AC power source supply signal voltage's amount only.6. The systems of claims 1, 2, 3, 4, or 5 wherein: a low frequency passfilter circuit is operatively connected between the low frequency ACpower source and the full rectifier circuit for simultaneously supplyingthe circuit and protecting the AC power source against reverse highfrequency signals.
 7. A start enforcer system for securing the “highinput voltage/large impedance load” worse case self supply starttriggering process status of a power management controller circuit thatdrives a converter circuit, the controller circuit receiving initiallyits minimum supply voltage from an off-line voltage source until thecontroller circuit is able to provide itself a strong enough signal formaintaining in a safe range its supply voltage and the controllercircuit having the self supply start triggering process reliantsimultaneously on several internal and/or external sub-circuits behaviorsuch as; a resistive circuit properly and efficiently sized forproviding the required minimum supply voltage to the controller circuitwhen the off-line voltage source reaches its minimum amount and/or theresistive circuit is properly and efficiently sized for not damaging thecontroller circuit when the off-line voltage source reaches its maximumvoltage amount, operatively coupled to the controller circuit's supplyelectrode; a capacitive circuit properly sized for maintaining thecontroller circuit's supply voltage within the controller circuit'srequired range despite large variations of the controller's outputsignal's duty cycle, operatively connected across the controller'ssupply electrodes; an under voltage lockout with hysteresis sub-circuitrequiring a minimum supply voltage for allowing the controller circuitto start delivering a square wave output signal and also the undervoltage lockout with hysteresis sub-circuit being able to shut down thecontroller circuit's output when the controller circuit's supply voltageis lower than a pre-established voltage amount; a voltage erroramplifier feedback sub-circuit having a feedback input operativelyconnected to the converter circuit's output, the converter circuit'soutput voltage amount increasing initially in a direct proportionalratio to the off-line source voltage amount and the voltage erroramplifier feedback sub-circuit being capable to decrees the controlleroutput signal duty cycle ratio when the converter circuit's outputvoltage reaches high amounts; a compensation capacitor circuitoperatively connected between the voltage error amplifier output andfeedback input, for allowing the voltage error amplifier feedbacksub-circuit amplify the feedback input's average voltage only; aswitching voltage source sub-circuit having a low impedance output andbeing able to provide a near zero voltage level in respect to thefeedback input's voltage amount during the time when the under voltagelockout with hysteresis sub-circuit do not allows the controller circuitto deliver its output signal and the low impedance output being alsoable to provide a voltage higher in amount than the feedback input'smaximum voltage when the voltage lockout with hysteresis sub-circuitallows the controller circuit to start delivering the square wave outputsignal; and a large impedance load allowing high voltage across theconverter circuit's output, the high voltage amount across the convertercircuit's output forcing the controller circuit, via the voltage erroramplifier feedback sub-circuit and the compensation capacitor circuit,to decrease and maintain the output signal duty cycle ratio down to avalue that is not strong enough for maintaining in a safe range thesupply voltage of the controller circuit; the system comprising: asemiconductor diode having a pre-established threshold voltage acrossits terminals, operatively connected into the circuit of the voltageerror amplifier sub-circuit's feedback input and the switching voltagesource sub-circuit's low impedance output, for decreasing for a shortperiod of time the voltage error amplifier sub-circuit's feedbackinput's voltage amount during the time when the under voltage lockoutwith hysteresis sub-circuit does not allows the controller circuit tostart delivering an output signal and the semiconductor diode havingvery large impedance in a reverse position when the switching voltagesource sub-circuit switches its status from near zero voltage level upto a voltage higher in amount than the feedback input's maximum voltage;and a resistive circuit properly sized and operatively coupled in serieswith the semiconductor diode for setting a precise maximum voltageamount at the voltage error amplifier's feedback input during the timewhen the under voltage lockout with hysteresis sub-circuit does notallows the controller circuit to deliver its output signal, forsecuring, together with the semiconductor diode, a large enough dutycycle ratio output signal and/or a strong enough output signal capableto maintain the controller circuit in a safe supply voltage range assoon as the under voltage lockout with hysteresis sub-circuit allows thecontroller circuit to deliver its output signal.
 8. The systems ofclaims 7 further comprising: one or more semiconductor diodes having apre-established threshold voltage, operatively connected into thecircuit of the voltage error amplifier feedback sub-circuit's feedbackinput and the switching voltage source sub-circuit's low impedanceoutput for decreasing the voltage error amplifier feedback sub-circuit'sfeedback input's voltage amount during the time when the under voltagelockout with hysteresis sub-circuit does not allows the controllercircuit to start delivering an output signal and the two or moresemiconductor diodes having very large impedance in a reverse positionwhen the switching voltage source sub-circuit switches its status fromnear zero voltage level up to a voltage higher in amount than thefeedback input's maximum voltage, for securing a large enough duty cycleratio output signal and/or a strong enough output signal capable tomaintain the controller circuit in a safe supply voltage range as soonas the under voltage lockout with hysteresis sub-circuit allows thecontroller circuit to deliver its output signal.
 9. The systems ofclaims 7 comprising: a voltage limiting circuit including a group ofdevices such as diodes and/or zener diodes and/or reference voltagesources and/or operational amplifiers, operatively connected into thecircuit of the voltage error amplifier feedback sub-circuit's input andthe switching voltage source sub-circuit's low impedance output fordecreasing the voltage error amplifier feedback sub-circuit's feedbackinput's voltage amount during the time when the under voltage lockoutwith hysteresis sub-circuit does not allows the controller circuit tostart delivering an output signal and the voltage limiting circuithaving very large impedance in a reverse position when the switchingvoltage source sub-circuit switches its status from near zero voltagelevel up to a voltage higher in amount than the feedback input's maximumvoltage, for securing a large enough duty cycle ratio output signaland/or a strong enough output signal capable to maintain the controllercircuit in a safe supply voltage range as soon as the under voltagelockout with hysteresis sub-circuit allows the controller circuit todeliver its output signal.
 10. A pulse width modulation controllersystem for driving a power factor correction converter circuit includingat least three devices such as a controllable power switch, anoscillating inductor and a high frequency rectifier diode, theoscillating inductor having a charging time and a discharging time andthe oscillating inductor being properly sized so that the momentarycurrent amount of the inductor increases linearly and directproportional with its supply voltage and/or its the charging timeamount, the converter circuit being supply by a low frequency AC powersource that provided a supply signal having cycles and semi-cycles via abridge rectifier circuit having at least a positive output and anegative output and the converter circuit delivering a rectified highfrequency supply signal to a complex load circuit, the complex loadcomprising at least one storing capacitive circuit and the controllersystem being capable to provide the converter circuit with a pulse widthmodulation driving signal consisting of trains of pulses constant infrequency and duty cycle during a period of time equal or longer thanone of the AC power source supply signal semi-cycle period, comprising:eight in/out electrodes including: a positive voltage input supplyelectrode operatively connected to a DC supply voltage source placedexternally to the controller system, the DC supply voltage source beinga classic power supply providing a stabilized and properly sized voltageamount or the DC supply voltage source being a self supply voltagesource that provides a voltage amount proportional to the controllersystem's pulse width modulation driving signal's duty cycle ratio andthe DC supply voltage source comprising a properly sized large valuefiltrating capacitor able to reasonably stabilize the supply voltagedelivered to the positive voltage input supply electrode, after thelarge value filtrating capacitor is fully charged; a negative voltage orcommon supply electrode operatively connected to the DC voltage source;a soft start electrode operatively connected, in respect to the commonsupply electrode, to a capacitive circuit placed externally to thecontroller system; a driving electrode operatively connected to thepower switch, for delivering the controller system's pulse widthmodulation driving signal; a current sensing electrode operativelyconnected to the power switch for sensing the momentary current amountof the power switch and/or for sensing the momentary current amount ofother circuits; a feedback electrode having a maximum feedback voltagethreshold operatively connected to the complex load and/or othercircuits, for sensing an error signal proportional to the momentaryvoltage amount across the load and/or across other circuits; acompensation electrode for allowing the attachment of frequencycompensation circuitries comprising at least a properly sizedcompensation capacitive circuit placed externally to the controllersystem operatively connected to the feedback electrode for securing thedelivery of the trains of pulses constant in frequency and duty cycleduring a period of time equal or longer than one of the AC power sourcesupply signal semi-cycle period, the compensation electrode alsoallowing external adjustments and/or limitations of the controllersystem's pulse width modulation driving signal's duty cycle ratio; a nonlinearity correction electrode operatively connected, to the bridgerectifier circuit's output, for sensing the momentarily amount of theconverter circuit's input supply voltage; the controller systemcomprising thirteen sub-circuits such as; an internal supply andprotection sub-circuit coupled to the positive input supply electrodeoperatively coupled with other controller system's sub-circuits forproviding to the controller system with all standard over voltage and/orunder voltage lockout with hysteresis circuitry that shuts down thepulse width modulation driving signal when the external DC supplyvoltage source provides a voltage amount higher or lower than apre-established range; a driver sub-circuit having an input and anoutput for amplifying, buffering and delivering the controller system'spulse width modulation signal to the power switch via the drivingelectrode, the driver sub-circuit receiving its supply voltage directlyfrom the positive voltage input supply electrode or the driver circuitreceiving its supply voltage via the internal supply and protectionsub-circuit; a voltage references sub-circuit receiving its supplyvoltage directly from the positive voltage input supply electrode or thevoltage references circuit receiving its supply voltage via the internalsupply and protection sub-circuit, for providing to the controller asmore as needed precise reference voltage sources and the voltagereferences sub-circuit comprising at least one low impedance outputswitching voltage source able to provide a near zero voltage level inrespect to the feedback input's voltage amount during the time when theunder voltage lockout with hysteresis sub-circuit does not allows thecontroller circuit to output its driving signal and the low impedanceoutput switching voltage source being also able to provide a voltagehigher in amount than the feedback input's maximum voltage thresholdwhen the voltage lockout with hysteresis sub-circuit allows thecontroller system to output its the driving signal; a fixed frequencyoscillator circuit having a set logic output, a reset logic output, aclock logic output and a voltage ramp input/output terminal, forproviding synchronized square and voltage ramp signals, the voltage rampsignals comprising waves having rising periods and decaying periods; acurrent limiter sub-circuit having an inverting input a non-invertinginput and a logic output, the inverting input being operativelyconnected to one reference voltage source of the voltage referencessub-circuit and the non-inverting input being coupled to the currentsensing electrode, for the current limiter sub-circuit to reverse itsoutput logic status, when the current amount sensed at the currentsensing electrode is higher than a pre-established amount; a pulse widthmodulation logic sub-circuit capable to generate a pulse widthmodulation signal comprising: a logic output operatively connected tothe driver sub-circuit input for amplifying or buffering the pulse widthmodulation signal; a first shut down logic input operatively coupled tothe internal supply and protection sub-circuit for shutting down thepulse with modulation signal when the external DC voltage sourceprovides a voltage amount higher or lower than a pre-established range;a second shut down logic input operatively connected to the currentlimiter sub-circuit's logic output for shutting down the pulse withmodulation signal when the current amount sensed at the current sensingelectrode is higher than a pre-established amount; a reset logic input,for terminating each the driving pulse; a set logic input operativelyconnected to the oscillator's set output, for validating the inceptionof each the driving pulse and the reset logic input must be already inits inactive and/or zero logic state when the set logic input is activeand/or zero logic, for allowing the next and only one driving pulseduring one the oscillator's complete cycle; a voltage error amplifiersub-circuit having an inverting input, a non-inverting input and a sinkonly analogic output, the sink only analogic output being coupled to thecompensation electrode, the non-inverting input being operativelyconnected to one reference voltage source of the voltage referencessub-circuit, and the inverting input being coupled to the feedbackelectrode, for amplifying the error signal collected at the feedbackelectrode, so that the controller system's pulse width modulationdriving signal's duty cycle to be contingent and direct proportional tothe momentary voltage amount reached at the compensation electrode; avoltage limiter sub-circuit having an input and an output, comprising; aconstant current source operatively coupled between the low impedanceoutput switching voltage reference source and the compensation electrodefor simultaneously supplying the voltage error amplifier's sink onlyoutput and also for allowing parallel voltage adjustments of othercircuits placed externally to the controller system; a zener diodeoperatively connected across the voltage limiter sub-circuit's output,for limiting at a pre-established maximum voltage amount the voltagelimiter sub-circuit's output signal, so that the pre-established maximumvoltage amount clamped at the output of the voltage limitersub-circuit's output to determine the maximum duty cycle ratio of thecontroller system's pulse width modulation driving signal; and a currentlimitation circuitry comprising diodes and resistive circuitsoperatively coupled between the input and the output terminals of thevoltage limiter sub-circuit, for reducing the noise and optimizing thein/out signal transfer; an analog reset voltage ramp driver sub-circuitcomprising: a voltage ramp buffer circuit for amplifying, under largeinput impedance, the current of the oscillators sub circuit's voltageramp signal; and an analog reset switching system operatively connectedto the clock logic output of the oscillator sub-circuit for decreasingrapidly near zero the voltage ramp signal's voltage amount, outputted bythe buffer circuit, during each time during the voltage ramp signalreaches is decaying period; a pulse width modulation comparatorsub-circuit having an inverting input, a non-inverting input and a logicoutput, the logic output being coupled to the reset input of the pulsewidth modulation logic sub-circuit, the inverting input beingoperatively connected to the output of the voltage limiter sub-circuitand the non-inverting input being coupled to the output of the analogreset voltage ramp driver sub-circuit, for resting periodically thepulse width modulation logic sub-circuit, so that the controllersystem's pulse width modulation driving signal's duty cycle to becontingent and direct proportional to the momentary voltage amountoutputted by the voltage limiter sub-circuit in respect to the to themomentary voltage amount delivered by the analog reset voltage rampdriver sub-circuit's output and also for the pulse width modulationcomparator sub-circuit to be reset and/or forced to commute fast to zeroits logic output status, each time during the voltage ramp signalreaches is decaying period, the decaying period lasting for at least aslong time as a reasonable low cost comparator circuit needs for itsoutput's high/low commutation's transit period; a soft start sub-circuithaving soft start input, a commutation input and a soft start output,the soft start output being coupled to the compensation electrode, thecommutation input being operatively connected to the low impedanceoutput switching voltage reference source and the soft start input beingcoupled via the soft start electrode to a soft start capacitive circuitplaced externally to the controller system, the soft start capacitivecircuit being properly sized and operatively connected to the soft startelectrode with respect to the common supply electrode for forcing asmooth increase of the soft start electrodes voltage amount, the softstart sub-circuit comprising a classic one transistor, one resistor, onediode circuitry for forcing the signal's voltage at the compensationelectrode to increase as smooth as the soft start electrode signal'svoltage, so that the pulse width modulation driving signal's duty cycleratio to increase smooth and safe; a start enforcer sub-circuit, havingan input coupled to the low impedance output switching voltage referencesource and an output coupled to the feedback input, for securing theworse self supply start triggering process case when initially thecontroller system is not able to provide a driving signal having a dutycycle ratio large enough for maintaining in a safe range its the DCsupply voltage amount and the internal supply and protection sub-circuitshuts down the controller system's driving signal when the DC supplyvoltage amount is lower than a pre-established range comprising: asemiconductor diodes accepting a pre-established threshold voltageacross its terminals, operatively connected into the circuit of thevoltage error amplifier sub-circuit's feedback input and the switchingvoltage source sub-circuit's low impedance output, for decreasing thevoltage error amplifier sub-circuit's feedback input's voltage amountand implicitly increasing the driving pulse signal duty cycle ratiountil the large value filtrating capacitor is fully charged and able toreasonably stabilize the supply voltage delivered to the positivevoltage input supply electrode despite large variations of the drivingpulses signal duty cycle and the semiconductor diode having very largeimpedance in a reverse current circuit, for releasing the feedbackelectrode of any voltage limitation when the switching voltage sourcesub-circuit switches its status from near zero voltage level up to avoltage higher in amount than the maximum feedback voltage thresholdamount; and a resistive circuit properly sized and operatively coupledin series with the semiconductor diode for setting a precise startenforcing voltage amount at the feedback electrode; and a non linearitycorrection sub-circuit for correcting the controller system's drivingsignal's duty cycle ratio in critical situations when the convertercircuit's input supply voltage momentary amount exceeds half of thevoltage amount across the load, the non linearity correction sub-circuithaving an inverting input, a non-inverting input and a sink onlyanalogic output, the sink only analogic output being coupled to thecompensation electrode, the non-inverting input being operativelyconnected to the feedback electrode, and the inverting input beingcoupled to the non linearity correction electrode, for amplifying, inrespect to a variable reference voltage which is actually the momentaryvoltage amount of the feedback electrode, a pre-established fraction ofthe converter circuit's input supply voltage, so that the controllersystem's pulse width modulation driving signal's duty cycle ratio to bereduced only when/if the momentary amount of the converter circuit'sinput supply voltage reaches high values that exceed half of the voltageamount across the load and/or the controller system's pulse widthmodulation driving signal's duty cycle ratio to be reduced down to zeroin the most critical boost converter's situation when the convertercircuit's input supply voltage momentary amount reaches or exceeds thevoltage amount across the load.
 11. The controller systems of claim 10comprising a number of fourteen electrodes that includes, besides theeight electrodes, another six electrodes, comprising: a voltagereference electrode coupled to the voltage reference sub-circuit's lowimpedance output switching voltage source for providing high precisionreference voltage and/or switching operations circuitry to othercircuits placed externally to the controller system; an oscillatorinput/output electrode coupled to the fixed frequency oscillatorsub-circuit's voltage ramp i/o terminal for allowing a full control ofthe oscillator sub-circuit's main parameters by the means of othercircuits placed externally to the controller system; a current sensingelectrode coupled to one of the pulse width modulation comparatorsub-circuit's input for allowing the control of the output drivingsignal duty cycle ratio by the means of other circuits placed externallyto the controller system; a synchronization electrode operativelycoupled to one of the fixed frequency oscillator sub-circuit's terminalsand/or one of the pulse width modulation sub-circuit' terminals forallowing in/out synchronization circuitry between the controller systemand other circuits placed externally to the controller system; a shutdown/protection electrode operatively coupled to one of the pulse widthmodulation logic sub-circuit' terminals for allowing shut/downprotection circuitry between the controller system and other circuitsplaced externally to the controller system; and a second drivingelectrode operatively connected to the power switch, for delivering asecond driving signal that can be similar or in opposite phase inrespect to the driving electrode's signal, so that the controller systemto be able to drive simultaneously two circuits such as the controllablepower switch.
 12. The controller systems of claims 10 comprisingexternally any combinations and/or arrangements of three to fourteenelectrodes and internally any combination and/or arrangements of atleast three from the total of thirteen functional blocks, including atleast one Analog Reset circuit and/or a Start Enforcer circuit and/or aNon Linearity Correction circuit.
 13. The controller systems of claim 10wherein which one or all amplifiers and or comparators sub-circuits mayhave their inverting and non-inverting inputs connected opposite way, inorder to respect the logic of a specific architecture of the pulse widthmodulation sub-circuit and or the oscillator sub-circuit.
 14. Thecontroller systems of claim 10 wherein which: the current limitationelectrode is coupled to the pulse width modulation comparator subcircuit's positive and/or current reading input.
 15. The controllersystems of claim 10 wherein which: the non linearity correctionsub-circuit delivers a signal in phase with the converter circuit'sinput supply voltage and the non linearity correction sub-circuit'soutput is coupled to the pulse width modulation comparator sub circuit'spositive and/or current reading input.
 16. The controller systems ofclaim 10 wherein which: the analog reset voltage ramp driver sub-circuitincludes; a voltage ramp buffer circuit for amplifying, under largeinput impedance, the current of the oscillators sub circuit's voltageramp signal; and an analog reset switching circuitry, placed externallyto the voltage ramp buffer circuit, the analog reset switching circuitryis operatively connected to the oscillator sub-circuit and or the pulsewidth modulation logic sub-circuit, for decreasing rapidly near zero thevoltage ramp signal's voltage amount, inputted by the pulse widthmodulation comparator sub-circuit, each time during the voltage rampsignal reaches is decaying period, so that the pulse width modulationcomparator sub-circuit's output to be reset fast back to its initiallogic state.
 17. The controller systems of claim 10 wherein which: thepulse width modulation comparator sub-circuit is replaced by an analogreset comparator sub-circuit; and the pulse width modulation logicsub-circuit is replaced by an analog reset pulse width modulation logicsub-circuit, for the pulse width modulation comparator sub-circuit'soutput to be reset fast back to its initial logic state, each timeduring the voltage ramp signal reaches is decaying period.
 18. Thecontroller systems of claim 10 in which the pulse width modulationcontroller system has eight in/out electrodes such as: a negativevoltage or common supply electrode; a positive voltage input supplyelectrode that is able to perform also as a protection electrode; adriver electrode for outputting a pulse width modulation controllingsignal; a feedback electrode for controlling the output signal's dutycycle ratio able to accept the attachment of a start enforcer circuit; acompensation electrode that allows external compensation of the feedbackcontrol circuits and also allows for a direct control of the outputdriving signal and or an internal soft start circuit; a current sensingelectrode that could be used also as a Non Linearity Correction orMaximum Duty Cycle pre-setting electrode and or as a Analog Resetelectrode; a voltage reference output electrode for supplying externalcircuits, able to perform also as a protection and/or switchingelectrode; and an oscillator controlling electrode able to perform alsoas a synchronization electrode.
 19. A non linearity correction systemfor improving the shape of the current absorbed by a controllableconverter circuit from an AC power source, by means of reducingperiodically the duty cycle ratio of the driving signal provided by apulse width modulation controller circuit having a feedback input, acompensation input and a driving output to the controllable convertercircuit during the time when the AC power source's momentarily voltageamount is higher than a pre-established amount, comprising: a sink onlyoutput operational amplifier having its output coupled to thecompensation input of the controller circuit for reducing periodicallythe duty cycle ratio of the driving signal; a classic two resistors andone capacitor fix gain and compensation circuit for the amplifier; a nonlinearity correction reference input that is coupled to a fix referencevoltage or the non linearity correction reference input is coupled tothe feedback input of the controller circuit for setting the voltagethreshold from where the operational amplifier starts correcting thedriving signal; and a non linearity correction input controlling inopposite phase the operational amplifier's output, the non linearitycorrection input is operatively connected to the AC power source forsensing the power source voltage amount and for progressively reducingthe duty cycle ratio of the driving signal in respect to the nonlinearity correction reference input's voltage amount.
 20. A nonlinearity correction system of claim 19 wherein the duty cycle ratio ofthe driving signal is periodically reduced using the controller'sinternal error amplifier by the means of resistive circuits operativelyconnected from the AC power source to the controller's feedback andcompensation inputs external circuit.
 21. A non linearity correctionsystem of claim 19 wherein the controller circuit has also a currentsense input and the duty cycle ratio is periodically reduced by themeans of resistive circuits operatively connected from the AC powersource to the controller's current sense input's external circuit. 22.An analog reset system for improving the performances of mixed signalcircuits and for achieving a smooth control of shorter output pulsesfrom voltage mode pulse width modulators wherein the analog comparatorscommutation speed is lower than the logic gates speed, comprising: aclassic mixed signal oscillator circuit comprising two comparators aflip-flop and a charge/discharge circuitry that is able to provide threesynchronized output signals including: a voltage ramp output signalhaving an ascendant period and a descendent period; a square wave outputClock signal comprising pulses that last only during the ascendantperiod of the voltage ramp signal; and a square wave output Set signalcomprising pulses that last only during the descendant period of thevoltage ramp signal; a voltage ramp driver circuit operatively connectedto the oscillator circuit for buffering the voltage ramp signal and thevoltage ramp driver circuit operatively coupled to the oscillator'sClock signal output for reducing near zero the amplitude of the voltageramp signal during its descendent period; a comparator circuit havingits inputs operatively connected to the voltage ramp driver circuit anda variable voltage source for a smoothly control of its output signalduty cycle ratio and also for the comparator to have enough time toreset its output back to its initial logic state during the time whenthe voltage ramp driver keeps near zero the amplitude of the voltageramp signal; and a classic three NOR gates pulse with modulation logiccircuit operatively connected to the comparator's output and the pulsewidth modulation logic circuit being also operatively connected with theset output of the oscillator for securing not more than one output pulseper each the voltage ramp signal cycle.
 23. The analog reset system ofclaim 22 wherein the set output signal rests directly the comparator andthe voltage ramp driver circuit is a buffer.
 24. The analog reset systemof claim 22 wherein the comparator receives the reset signal from thepulse width modulation circuit and the voltage ramp driver circuit is abuffer.
 25. The analog reset system of claim 22 wherein the comparatorreceives a modified voltage ramp signal having its amplitude near zeroduring its sad descendent period, directly from the oscillatoreliminating the need of a voltage ramp driver circuit and/orsynchronized square wave signal.
 26. The analog reset system of claim 22wherein a hybrid circuit including: a classic current mode pulse widthmodulation controller, such as UC384, is capable of providing theoscillator, comparator and pulse width modulation circuits; and anexternal discrete parts circuit provides the voltage ramp driver and thecomparator reset synchronization circuitry.
 27. A method of constantpulse proportional current mode of operations for a power factorcorrection system that improves near unity the electrical energytransfer's power factor parameter in a low frequency AC power source toa complex load circuit, the system including a low frequency AC powersource, a full rectifier circuit, a controllable high frequency DC/DCconverter, a complex load including at least a storing capacitor circuitand high frequency pulse width modulation controller circuit,comprising: rectifying the low frequency AC power source signal using afull rectifier circuit that provides a fully rectified supply signal;converting the fully rectified signal using the high frequencycontrollable DC/DC converter into a rectified high frequency supplysignal; storing electrical using the storage capacitor of the complexload; eliminating the direct current between the full rectifier circuitand the complex load using either an appropriated converter topographysuch as buck boost or a high frequency supply signal strong enough forkeeping the DC voltage across the complex load higher in amount then theAC power source peak voltage; and controlling the DC/DC converter with aproper driving pulse signal consisting of trains of pulses constant infrequency and duty cycle during a time equal or longer than onesemi-cycle period of the AC power source supply signal so that thecurrent amount absorbed by the DC/DC converter from the AC power sourceis contingent and linearly proportional to the AC power source supplysignal voltage's amount only.
 28. The method of claim 27 wherein a lowfrequency pass filter circuit is operatively connected between the lowfrequency AC power source and the full rectifier circuit forsimultaneously supplying the circuit and protecting the AC power sourceagainst reverse high frequency signals.
 29. The method of claim 27wherein keeping constant the main parameters of the high frequencycontrolling signal such as amplitude, frequency and duty cycle the powerfactor is greater than 0.999, the THD is lower than 1% and theefficiency of the entire system is over 95%.
 30. A method of analogreset for improving the performances of mixed signal circuits and forachieving a smooth control of shorter output pulses from voltage modepulse width modulators wherein the analog comparators commutation speedis lower than the logic gates speed, system including a classic mixedsignal oscillator circuit having an ascendant period and a descendentperiod, a voltage ramp driving circuit, a pulse width modulationcomparator circuit and a pulse width modulation logic circuit,comprising: generating a voltage ramp signal and at least onesynchronized square wave signal using the classic mixed signaloscillator; buffering the voltage ramp signal using the voltage rampdriving circuit; comparing the voltage ramp signal with a referencevoltage and outputting a variable duty cycle square wave using acomparator circuit; securing not more than one output pulse per voltageramp signal's cycle using a typical three NOR gate pulse with modulationlogic circuit; and resetting the pulse width modulation comparatorsoutput logic state during each of the voltage ramp signal's cycle usinga synchronized signal incoming from the oscillator circuit or pulsewidth modulation circuit.
 31. The method of claim 30 wherein thecomparator receives a modified voltage ramp signal having its amplitudenear zero during its said descendent period, directly from theoscillator eliminating the need of a voltage ramp driver circuit and/orsynchronized square wave signal.
 32. A method of non linearitycorrection for improving the shape of the current absorbed by acontrollable converter circuit from an AC power source, by means ofreducing periodically the duty cycle ratio of the driving signalprovided by a pulse width modulation controller circuit having aoperational amplifier including a feedback input a reference input and acompensation output operatively connected for decreasing the duty cycleratio of a driving output that provides a pulse width modulation signalto the controllable converter circuit during the time when the AC powersource's momentarily voltage amount is higher than a pre-establishedamount, comprising: sensing the AC power source's supply signal using aresistive divider circuit connected to one input of a operationalamplifier; comparing aid AC power source's supply signal amount to areference voltage coupled to the other input of the operationalamplifier; and decreasing periodically the duty cycle ratio of thedriving output signal only when the AC power source's supply signalamount is higher that a pre-established reference using a proper gainand compensation circuit for the operational amplifier.
 33. A method ofstart enforcement for securing the “high input voltage/large impedanceload” worse case self supply start triggering process status of a powermanagement controller circuit that drives a converter circuit, thecontroller circuit receiving initially its minimum supply voltage froman off-line voltage source until the controller circuit is able toprovide itself a strong enough signal for maintaining in a safe rangeits supply voltage, comprising: keeping the feedback input of thecontroller circuit at a pre-established safe voltage amount before thecontroller start supplying itself using at least one switch andresistive circuits for allowing a large enough start up output drivingpulse; and releasing completely the feedback input of the controllercircuit as soon the controller start supplying itself using at least onediode and any electronic switching system including low impedanceswitching voltage references able to provide a voltage higher in amountthan the peak voltage at the feedback input.
 34. A method for transferof electrical energy between a low frequency AC power source and acomplex load, the method comprising the steps of: converting a signalfrom the AC power source into a low frequency fully rectified supplysignal; converting the low frequency fully rectified supply signal intoa DC voltage across the complex load; and providing a plurality oftrains, wherein each train includes a plurality of pulses having anearly constant duty cycle and frequency.
 35. A system for transfer ofelectrical energy between a low frequency AC power source and a complexload, the system comprising: a bridge rectifier circuit operativelyconnected to the AC power source for converting a signal from the ACpower source into a low frequency fully rectified supply signal; acomplex load coupled to the bridge rectifier; a boost converter unitoperatively coupled to the bridge rectifier and the complex load forconverting the low frequency fully rectified supply signal into a DCvoltage across the complex load; and a high frequency controller circuitcoupled to the boost converter for providing a plurality of trains,wherein each train includes a plurality of pulses having a nearlyconstant duty cycle and frequency.
 36. The system of claim 35 whereinthe bridge rectifier is a four diode bridge rectifier having a negativeoutput and a positive output.
 37. The system of claim 36 wherein thecomplex load comprises at least one storage capacitive circuit having apositive end and a negative end and wherein the negative end of thecomplex load is coupled to the negative output of the bridge rectifier.38. The system of claim 35 wherein the DC voltage across the complexload is higher in amount than the bridge rectifier peak voltage amountfor eliminating any direct current between the bridge rectifier and thecomplex load.
 39. The system of claims 38 wherein the boost converterunit is a controllable high frequency pulse width modulation boostconverter unit.
 40. The system of claim 39 wherein the boost converterunit comprises: a capacitive circuit coupled across the output of therectifier bridge, for having high impedance in respect to the AC powersource low frequency supply signal and low impedance in respect to theboost converter high frequency signal; a high frequency rectifier diodecoupled to the complex load, wherein the high frequency rectifier diodeincludes: an anode; and a cathode, wherein the cathode of the highfrequency rectifier diode is coupled to the positive end of the complexload; an oscillating inductor coupled at one end to the positive outputof the bridge rectifier and at the other end to the anode of the highfrequency rectifier diode, wherein the inductor includes: a chargingtime; and a discharging time; and a controllable power switch circuitcoupled at one end to the oscillating inductor and the anode of the highfrequency rectifier diode and at the other end to the negative pole ofthe bridge rectifier for periodically charging the oscillating inductor.41. The system of claim 40 wherein the oscillating inductor is properlysized so that the momentary current amount across the inductor increasesin direct proportional with its supply voltage and/or its charging timeamount and for delivering to the complex load a high frequency pulselarge signal during its discharging time.
 42. The system of claim 41wherein periodically charging of the oscillating inductor is inaccordance with a high frequency driving pulse signal.
 43. The system ofclaim 40 wherein the high frequency controller circuit provides thecontrollable switch with a proper driving pulse signal comprising trainsof pulses that are constant in frequency and duty cycle during a time sothat the current amount absorbed by the boost converter from the ACpower source is contingent and linearly proportional to the AC powersource supply signal voltage when the amount of the voltage amountacross the complex load is maintained higher than the bridge rectifierpeak voltage amount.
 44. The system of claim 43 wherein the time ofdriving the trains of pulses is equal to one semi-cycle period of the ACpower source supply waves.
 45. The system of claim 44 wherein the timeof driving the trains of pulses is longer than one semi-cycle period ofthe AC power source supply waves.
 46. The system of claim 45 wherein thecomplex load comprises at least one storage capacitive circuit having apositive end and a negative end and wherein the negative end of thecomplex load is coupled to the positive output of the bridge rectifier.47. The system of claim 35 wherein the boost converter unit is acontrollable high frequency pulse width modulation buck-boost converter.48. The system of claim 47 wherein the buck-boost converter comprises: acapacitive circuit coupled across the output of the rectifier bridge,properly sized for having high impedance in respect to the AC powersource low frequency supply signal and low impedance in respect to theboost converter high frequency signal. a high frequency rectifier diodehaving an anode and a cathode and the cathode of the high frequencyrectifier diode is coupled to the positive end of the complex load; anoscillating inductor coupled at one end to the positive output of thebridge rectifier and at the other end to the anode of the high frequencyrectifier diode, the inductor having a charging time and a dischargingtime and the inductor being properly sized so that the momentary currentamount across the inductor increases linearly and direct proportionalwith its supply voltage and/or its charging time amount, for deliveringto the complex load a high frequency pulse large signal during itsdischarging time; and a controllable power switch circuit coupled at oneend to the oscillating inductor and the anode of the high frequencyrectifier diode and the switch is coupled at the other end to thenegative pole of the bridge rectifier for being able to periodicallycharge the oscillating inductor in accordance to a high frequencydriving pulse signal.
 49. The system of claim 35, wherein the boostconverter is a controllable high frequency pulse width modulation highefficiency snubber boost converter unit.
 50. The system of claim 49wherein the snubber boost converter unit comprises: a first capacitivecircuit coupled across the output of the rectifier bridge, properlysized for having high impedance in respect to the AC power source lowfrequency supply signal and low impedance in respect to the boostconverter high frequency signal; a first high frequency rectifier diodehaving an anode and a cathode and the cathode of the high frequencyrectifier diode is coupled to the positive end of the complex load; asecond high frequency rectifier diode having an anode and a cathode andthe cathode of the high frequency rectifier diode is coupled to thepositive end of the complex load; a third high frequency rectifier diodehaving an anode and a cathode and the anode of the high frequencyrectifier diode is coupled to the positive output of the bridgerectifier; a first oscillating inductor coupled at one end to thepositive output of the bridge rectifier and at the other end to theanode of the first high frequency rectifier diode, the inductor having acharging time and a discharging time and the inductor being properlysized so that the momentary current amount across the inductor increaseslinearly and direct proportional with its supply voltage and/or itscharging time amount, for delivering to the complex load a highfrequency pulse large signal during its discharging time; a secondoscillating inductor coupled at one end to the cathode of the third highfrequency rectifier diode and at the other end to the anode of thesecond high frequency rectifier diode, the inductor having a chargingtime and a discharging time and the inductor being properly sized sothat the momentary current amount across the inductor increases linearlyand direct proportional with its supply voltage and/or its charging timeamount, for delivering to the complex load a high frequency pulse largesignal during its discharging time; a controllable power switch circuithaving alternatively a ON and a OFF state coupled at one end to thefirst oscillating inductor and the anode of the first high frequencyrectifier diode and the switch is coupled at the other end to thenegative pole of the bridge rectifier for being able to periodicallycharge during its ON state the oscillating inductors in accordance to ahigh frequency driving pulse signal; and a second capacitive circuitcoupled at one end to the first inductor, the switch and the anode ofthe first high frequency rectifier diode and coupled at the other and tothe second inductor and the second high frequency rectifier diode,properly sized for increasing the efficiency of the converter by notallowing a too fast increased of the switch's voltage during its OFFperiod and the second capacitive circuit being also properly sized to donot negatively affect the high efficiency snubber converter circuit'slinearity in respect to the average current absorbed from the ACgenerator.
 51. The system of claim 35 wherein the bridge rectifierincludes a common output and wherein the complex load includes athree-terminal complex load having a positive end, a negative end and acommon end, wherein the common end is coupled to the common output ofthe bridge rectifier circuit to form the common connection of the powerfactor correction system.
 52. The method of claim 51 wherein the complexload comprises: a first storage capacitive circuit coupled across thepositive end and the common end of the three-terminal complex load; asecond storage capacitive circuit coupled across the negative end andthe common end of the three-terminal complex load; and a resistivecircuit coupled across the positive end and the negative end of thethree-terminal complex load.
 53. The method of claim 35 wherein theboost converter unit includes a controllable high frequency pulse widthmodulation voltage doubler boost converter circuit operatively coupledto the bridge rectifier and the complex load for converting the lowfrequency fully rectified supply signal into a DC voltage across thecomplex load higher in amount than the bridge rectifier peak voltageamount for eliminating any direct current between the bridge rectifierand the complex load.
 54. The method of claim 53 wherein the boostconverter further comprises: a first capacitive circuit coupled acrossthe positive output and the common output of the bridge rectifier, asecond capacitive circuit coupled across the negative output and thecommon output of the bridge rectifier, wherein the first and secondcapacitive circuit each have a high impedance relative to the AC powersource low frequency supply signal and a low impedance relative to theboost converter high frequency signal; a first high frequency rectifierdiode having an anode and a cathode wherein the cathode of the firsthigh frequency rectifier diode is coupled to the positive end of thecomplex load; a second high frequency rectifier diode having an anodeand a cathode wherein the anode of the second high frequency rectifierdiode is coupled to the negative end of the complex load; a firstoscillating inductor coupled at one end to the positive output of thebridge rectifier and at the other end to the anode of the first highfrequency rectifier diode; a second oscillating inductor coupled at oneend to the negative output of the bridge rectifier and at the other endto the cathode of the second high frequency rectifier diode; a firstcontrollable power switch circuit coupled at one end to the firstoscillating inductor and the anode of the first high frequency rectifierdiode and the first controllable switch is coupled at the other end tothe common output of the bridge rectifier and also coupled to the commonend of the three terminals load for being able to periodically chargethe first oscillating inductor in accordance to a high frequency drivingpulse signal; a second controllable power switch circuit coupled at oneend to the second oscillating inductor and the cathode of the secondhigh frequency rectifier diode and the second controllable switch iscoupled at the other end to the common output of the bridge rectifierand also coupled to the common end of the three terminals load for beingable to periodically charge the second oscillating inductor inaccordance to a high frequency driving pulse signal; a high frequencydriving transformer comprising: a primary coil able to directly receiveand transfer simultaneously via magnetic field a pulse width modulationdriving pulse signal to the first and second controllable switches; afirst secondary coil operatively connected to the first controllableswitch; and a second secondary coil operatively connected to the secondcontrollable switch.
 55. The system of claim 53, wherein the firstinductor includes a charging time and a discharging time and wherein themomentary current amount across the first inductor increases linearlyand in direct proportion with its supply voltage or its charging timeamount, for delivering to the three terminals of the complex load a highfrequency pulse large signal during its discharging time.
 56. The systemof claim 54, wherein the first inductor includes a charging time and adischarging time and wherein the momentary current amount across thefirst inductor increases linearly and in direct proportion with itssupply voltage and its charging time amount, for delivering to the threeterminals of the complex load a high frequency pulse large signal duringits discharging time.
 57. The method of claim 54, wherein the secondinductor includes a charging time and a discharging time and wherein themomentary current amount across the second inductor increases linearlyand in direct proportional with its supply voltage or its charging timeamount, for delivering to the three terminals complex load a highfrequency pulse large signal during its discharging time.
 58. The methodof claim 54, wherein the second inductor includes a charging time and adischarging time and wherein the momentary current amount across thesecond inductor increases linearly and in direct proportional with itssupply voltage and its charging time amount, for delivering to the threeterminals complex load a high frequency pulse large signal during itsdischarging time.
 59. An apparatus for improving power factor correctionto near unity comprising a high frequency controller circuit coupledbetween a low frequency AC power source and a complex load, theapparatus comprising means for generating a plurality of trains, whereineach train includes a plurality of pulses having a nearly constant dutycycle and frequency during a time at least equal to one semi-cycleperiod of a supply signal of the AC power source.
 60. A method for powerfactor correction comprising the steps of fully rectifying a lowfrequency AC power source signal, controlling the fully rectified signalby pulse width modulation through the use of a pulse width modulationcontrol signal comprises a train of pulses having a substantiallyconstant frequency and a substantially constant duty cycle, and using ahigh frequency converter into a rectified high frequency supply signal,and applying the resulting DC signal to a complex load where the loadhas a capacitive storage component.
 61. The method of claim 60 furtherincluding the step of providing a DC/DC converter wherein currentabsorbed by the DC/DC converter from the AC power source is contingentupon and linearly proportional to the voltage of the AC power sourcesignal.
 62. A method for analog reset for improving the performances ofmixed signal circuits and for achieving a smooth control of shorteroutput pulses from voltage mode pulse width modulators wherein thecommutation speed of the analog comparator is lower than speed of anassociated logic gate, the method comprising the steps of: generating avoltage ramp signal and at least one synchronized square wave signal;buffering the voltage ramp signal using the voltage ramp drivingcircuit; comparing the voltage ramp signal with a reference voltage;outputting a variable duty cycle square wave using a comparator circuit;securing an output pulse per cycle of the voltage ramp signal using athree NOR gate pulse width modulation logic circuit; resetting theoutput logic state of the pulse width modulation logic circuit duringeach cycle of the voltage ramp signal using a synchronized signal 63.The method of claim 62 wherein the synchronized signal comes from anoscillator circuit.
 64. The method of claim 62 wherein the synchronizedsignal comes from the pulse width modulation circuit.
 65. The method ofclaim 62 further comprising the step of providing to the comparatorcircuit, directly from the oscillator, a modified voltage ramp signalhaving its amplitude near zero during its descendent period, therebyeliminating the need of a voltage ramp driver circuit and/orsynchronized square wave signal.
 66. A method of non-linear correctioncomprising the steps of: adapting the shape of current absorbed by acontrollable converter circuit from an AC power source; and reducingperiodically the duty cycle ratio of the driving signal provided by apulse width modulation controller circuit wherein the step of reducingincludes: altering a first voltage with a portion of a second voltage;and proportionally altering the controllable converter circuit's drivingpulses' duty cycle.
 67. The method of claim 66 wherein the controllercircuit includes an operational amplifier including a feedback input, areference input, and a compensation output operatively connected fordecreasing the duty cycle ratio of a driving output that provides apulse width modulation signal to the controllable converter circuitduring the time when the AC power source's momentarily voltage amount ishigher than a pre-established amount.
 68. The method of claim 67 furthercomprising the steps of: sensing the AC power source's supply signalusing a resistive divider circuit connected to one input of theoperational amplifier; comparing said AC power source's supply signalamount to a reference voltage coupled to the other input of theoperational amplifier; and decreasing periodically the duty cycle ratioof the driving output signal only when the AC power source's supplysignal amount is higher that a pre-established reference using a propergain and compensation circuit for the operational amplifier.